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| I5216 SERIES Advanced Information PRELIMINARY 8 TO 16 MINUTE VOICE RECORD/PLAYBACK SYSTEM WITH INTEGRATED CODEC GENERAL DESCRIPTION The ChipCorder I5216 is an 8 to 16 minute Voice and Data Record and Playback system with integrated Voice band CODEC. The device works on a single 2.7V to 3.3V supply, and has fully integrated system functions, including: AGC, microphone preamplifier, speaker driver, memory and CODEC. The CODEC meets the PCM conformance specification of the G.714 recommendation. Its Law and A-law compander meets the specification of the ITU-T G.711 recommendation. FEATURES * * * * * * * * * * * Single Supply 2.7 to 3.3 Volt operation Voice and digital data record and playback system on a single chip Industry-leading sound quality Low voltage operation Message management Fully integrated system functions Flexible architecture Nonvolatile message storage Configurable ChipCorder sampling rates of 4 kHz, 5.3kHz, 6.4 kHz and 8kHz 8, 10, 12 and 16 minutes duration External or internal Voice recorder clock serial interface (400kHz) Configurable analog paths 2.2V Microphone Bias Pin * I2C * * * * 100 year message retention (typical) 100K analog record cycles (typical) * 10K digital record cycles (typical) * Full-duplex (not in I2S mode) single channel speech CODEC with : o External 13.824 MHz, 27.648 MHz, 20.48 MHz or 40.96 MHz master clock o I2S and PCM digital audio interface ports o Serial transfer data rate from 64 to 3072 Kbps o Short and Long frame sync formats o 2s complement and signed magnitude data format o Complete -Law and A-Law companding o Linear 14 bit PCM CODEC-filter for A/D and D/A converter o 8 kHz or 44.1 kHz - 48 kHz digital audio sampling rate options o Analog receive and transmit gain adjust o Configurable setup through the I2C interface -1 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY TABLE OF CONTENTS GENERAL DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................................. 1 PIN LAYOUT & DESCRIPTIONS ............................................................................................ 4 I5216 BLOCK DIAGRAMS....................................................................................................... 6 FUNCTIONAL DESCRIPTION ................................................................................................ 8 SPEECH/SOUND QUALITY....................................................................................... 8 DURATION ................................................................................................................. 8 FLASH STORAGE...................................................................................................... 9 MICROCONTROLLER INTERFACE.......................................................................... 9 PROGRAMMING ........................................................................................................ 9 APPLICATIONS....................................................................................................................... 9 INTERNAL REGISTERS ....................................................................................................... 14 MEMORY ORGANIZATION .................................................................................................. 17 OPERATION MODES............................................................................................................ 17 I C PORT ............................................................................................................................... 17 I C SLAVE ADDRESS ........................................................................................................... 18 I C OPERATION DEFINITIONS ............................................................................................ 19 I C CONTROL REGISTERS.................................................................................................. 21 COMMAND BYTE.................................................................................................................. 21 FUNCTION BITS ................................................................................................................... 21 REGISTER BITS.................................................................................................................... 22 OPCODE SUMMARY ............................................................................................................ 22 DATABYTES.......................................................................................................................... 24 POWER-UP SEQUENCE..................................................................................................... 25 SET MASTER CLOCK DIVISION RATIO............................................................................. 25 PLAYBACK MODE ..................................................................................... ......................... 26 RECORD MODE...................................................................................................... ............ 26 FEED THROUGH MODE ........................................................................................ ............ 26 CALL RECORD ....................................................................................................... ............ 30 MEMO RECORD ..................................................................................................... ............ 31 MEMO & CALL PLAYBACK..................................................................................... ............ 32 MESSAGE CUEING ................................................................................................ ............ 34 ANALOG MODE ...................................................................................................... ............ 34 2 2 2 2 -2 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY AUTO MUTE & AUTO GAIN FUNCTIONS ............................................................. ............ 37 VOLUME CONTROL DESCRIPTION ..................................................................... ............ 38 SPEAKER & AUX OUT DESCRIPTION .................................................................. ............ 39 MICROPHONE INPUTS .......................................................................................... ............ 40 DIGITAL MODE ....................................................................................................... ............ 41 WRITING DATA.................................................................................................................... 41 READING DATA ................................................................................................................... 41 ERASING DATA ................................................................................................................... 41 EXAMPLE COMMAND SEQUENCES ................................................................................. 42 PIN DETAILS ........................................................................................................................ 45 DIGITAL I/O PINS.................................................................................................... 45 ANALOG I/O PINS................................................................................................... 48 AUXILIARY OUTPUT .............................................................................................. 49 AUXILIARY INPUT .................................................................................................. 50 POWER & GROUND PINS ..................................................................................... 51 SAMPLE LAYOUT FOR PDIP ................................................................................. 52 ELECTRICAL CHARACTERISTICS..................................................................................... 53 ABSOLUTE MAXIMUM RATINGS FOR PACKAGED PARTS................................ 53 ABSOLUTE MAXIMUM RATINGS FOR DIE........................................................... 53 OPERATING CONDITIONS FOR PACKAGED PARTS ......................................... 53 OPERATING CONDITIONS FOR DIE .................................................................... 54 GENERAL PARAMETERS ................................................................................................... 54 TIMING PARAMETERS........................................................................................................ 55 ANALOG PARAMETERS ..................................................................................................... 57 I C INTERFACE TIMING ...................................................................................................... 60 CODEC PARAMETERS ....................................................................................................... 61 TIMING DIAGRAMS ............................................................................................................. 62 I C SERIAL INTERFACE TECHNICAL INFORMATION ...................................................... 69 I S SERIAL INTERFACE TECHNICAL INFORMATION ...................................................... 73 DEVICE PHYSICAL DIMENSIONS ...................................................................................... 77 DIE BONDING PHYSICAL LAYOUT .................................................................................... 80 ORDERING INFORMATION................................................................................... 82 2 2 2 -3 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY ISD5216 Pin Layout VCCD SCL A1 SDA VSSA SDI SDIO RAC INT MCLK VCCD VCCD SCL A1 SDA A0 VSSD VSSD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 WS SCK NC AUX OUT AUX IN VCCA SP+ VSSA SPACAP MICBS MICMIC+ VSSA A0 VSSD VSSD VSSA MIC+ MICMICBS ACAP SPVSSA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 VCCD MCLK INT RAC SDIO SDI VSSA WS SCK NC AUX OUT AUX IN VCCA SP+ ISD5216 I5216 22 21 20 19 18 17 16 15 I5216 ISD5216 28 -PIN TSOP PDIP/SOIC PDIP VCCD SCL A1 SDA VSSD VSSD A0 MICBS MICMIC+ VSSA ACAP SPVSSA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 VCCD MCLK INT RAC SDIO VSSA SDI NC AUX OUT SCK WS AUX IN VCCA SP+ I5216 23 22 21 20 19 18 17 16 15 SOIC -4 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY PIN DESCRIPTION Pin Name Pin No. 28-pin TSOP 4 Pin No. 28-pin PDIP 25 Pin No. 28-pin SOIC 25 Functionality RAC /INT 5 26 26 MCLK 6 27 27 SCL SDA A0 A1 MIC+ MICMICBS ACAP SP+ SPAUX IN AUX OUT SDI SDIO WS SCK VCCD 9 11 12 10 16 17 18 19 22 20 24 25 2 3 28 27 7,8 2 4 5 3 9 10 11 12 15 13 17 18 23 24 21 20 1,28 2 4 7 3 10 9 8 12 15 13 17 20 22 24 18 19 1,28 VSSD VSSA VCCA 13,14 1,15,21 23 6,7 8,14,22 16 5,6 11,14,23 16 NC 1 26 19 21 Row Address Clock; an open drain output. The RAC pin goes LOW 1 TRACLO before the end of each row of memory, and returns HIGH at exactly the end of each row of memory. Interrupt Output; an open drain output indicating that a set EOM bit has been found during Playback, or that the chip is in an Overflow (OVF) condition. This pin remains LOW until a Read Status command is executed. This pin allows the internal clock of the Voice record/playback system to be externally driven for enhanced timing precision. This pin is grounded for most applications. It is required for the CODEC operation. 2 Serial Clock Line is part of the I C serial bus. It is used to clock the 2 data into and out of the I C interface. 2 Serial Data Line is part of the I C serial bus. Data is passed between devices on the bus over this line. 2 Input pin that supplies the LSB for the I C Slave Address. 2 Input pin that supplies the LSB +1 bit for the I C Slave Address. Differential positive Input to the microphone amplifier. Differential negative Input to the microphone amplifier. Microphone Bias Voltage AGC Capacitor connection. Required for the on-chip AGC amplifier. Differential Positive Speaker Driver Output. Differential Negative Speaker Driver Output. When the speaker outputs are in use, the AUX OUT output is disabled. Auxiliary Input. This is one of the gain adjustable analog inputs for the device. Auxiliary Output. This is one the analog outputs for the device. When this output is in use, the SP+ and SP- outputs are disabled. Serial Digital Audio PCM Input. 2 Serial Digital Audio PCM Output or I S Input/Output. 2 Digital audio PCM Frame sync (FS) or I S Word Sync (WS). 2 Digital audio PCM or I S Serial Clock. Positive Digital Supply pins. These pins carry noise generated by internal clocks in the chip. They must be carefully bypassed to Digital Ground to ensure correct device operation. Digital Ground pins. Analog Ground pins. Positive Analog Supply pin. This pin supplies the low level audio sections for the device. It should be carefully bypassed to Analog Ground to ensure correct device operation. No Connection See parameters section of the datasheet. Publication Release Date: November 30, 2001 Revision A1 -5 I5216 SERIES Advanced Information PRELIMINARY BLOCK DIAGRAMS I5216 Block Diagram MICBS MICROPHONE 2.2V Voltage reference 1 (AGPD) MIC+ MIC AGCCAP MIC IN INP SUM1 MUX AGC 1 2 SUM1 Summing AMP SUM1 ARRAY SUM1 FILTO AUX IN 2 Input Source MUX (AGPD) AUX IN Auto mute Auto gain 1 Low Pass Filter 1 ( S1M0 ) S1M1 FILTO SUM2 Summing AMP Filter MUX 1 (FLS0) (AMT0) (FLPD) ( S2M0) S2M1 1.0 / 1.4 / 2.0 / 2.8 SUM1 MUX AUX IN AUX IN AMP (INS0) 1 1 ARRAY Internal Clock (AXPD) DAO ( ) 2 ( AXG0) AXG1 /2 2 OSPD CKDV SUM2 ) 2( Multilevel Storage Array 2 FLD0 FLD1 ) (ANALOG) MCLK MIC+ MIC- ( S1S0 S1S1 2 x 64 S/H CTRL (DIGITAL) Array I/O Mux Program/Read Control FILTO AUX OUT AMP AUX OUT Output MUX A/D 2 x 64-bit reg. SUM2 VOL ARRAY OUT (DIGITAL) 1 (CKD2) ARRAY OUT (ANALOG) SPEAKER Spkr. AMP SP+ SP- DAO INP SUM2 SUM1 2 CODEC Mux INP DAO SUM2 Volume Control 1 (VLPD) 3 () CDI0 CDI1 2 () VOL0 VOL1 VOL2 ( OPS0 ) OPS1 2 Vol MUX ( OPA0 ) OPA1 -Law / A-Law / Linear 14 bit CODEC 2 ( VLS0 ) VLS1 (ADPD) DAPD 2 Power Conditioning PCM / I2S Interface Device Control VCCA VSSA VSSA VSSD VSSD VCCD VCCD WS SCK SDIO SDI SCL SDA INT RAC A0 A1 5/22/01 -6 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I5216 CODEC DIAGRAM /A-Law Expander or linear 14 bit Digital Smoothing Interpolation Filter 0.8/1/1.2/1.25/1.4/1.6/1.8/2 14 bit Digital Demodulator 1 bit 1 bit D/A & SC Filter 1 DAO ANALOG OUT 3 ( ANALOG IN LAW0 LAW1 ) 2 ( MUTE ) 1 (DAPD) ( COG0 COG1 COG2 ) Anti Aliasing Filter SC AMP 1 ( CIG0 CIG1 CIG2 ) (ADPD) Analog Modulator 1 bit 3 Digital Anti-Aliasing Decimation Filter ( MUTE ) 1 15 bit Digital High pass Filter HPF0 HSR0 14 bit Sample frequency 1 ( ) 2 ( LAW0 LAW1 ) 8 bits or 16 bits (I2S0) 1 /A-Law Compressor or linear (HSR0 ) Digital PLL WS PCM / I2S Interface 2 1 8 bits or 16 bits (CKD2 ) /2 1 WS SCK SDIO SDI MCLK 5/8/01 -7 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY FUNCTIONAL DESCRIPTION O The I5216 ChipCorder Product provides high quality, fully integrated, single-chip Record/Playback solutions for 8- to 16-minute messaging applications that are ideal for use in PBX systems, cellular phones, automotive communications, GPS/navigation systems, and other portable products. The I5216 product is an enhancement to the ISD5116 architecture, providing: 1) A full duplex Voice CODEC with 2 -Law and A-Law compander, with I S and PCM interface ports; 2) A 2.2V microphone bias supply for reduced noise coupling. This supply can also be used to power down the external microphone with the system. Analog functions and audio gating have also been integrated into the I5216 product to allow for easy interfacing with integrated chip sets on the market. Audio paths have been designed to enable full duplex conversation record, voice memo and answering machine (including outgoing message playback). Logic Interface Options of 2.0V and 3.0V are supported by the I5216 to accommodate both portable communication (2.0- and 3.0-volt required) and automotive product customers (5.0-volt required). Like other ChipCorder products, the I5216 integrates the sampling clock, anti-aliasing and smoothing filters, and multi-level storage array on a single chip. For enhanced voice features, the I5216 eliminates external circuitry by integrating automatic gain control (AGC), a power amplifier/speaker driver, volume control, summing amplifiers, analog switches, and a Voice CODEC. Input level adjustable amplifiers are also included, providing a flexible interface for multiple applications. Recordings are stored in on-chip nonvolatile memory cells, providing zero-power message storage. This unique, single-chip solution is made possible through Winbond's patented multilevel storage technology. Voice and audio signals are stored directly into solid-state memory in their natural, uncompressed form, providing superior quality voice and music reproduction. SPEECH/SOUND QUALITY The I5216 ChipCorder product can be configured, via software, to operate at 4.0, 5.3, 6.4, and 8.0 kHz sampling frequencies, allowing the user a choice of speech quality options. Increasing the duration decreases the sampling frequency and bandwidth, which affects sound quality. The "Input Sample Duration" table below compares filter pass band and product durations. DURATION To meet end-system requirements, the I5216 device is a single-chip solution, which provides 8 to 16 minutes of voice record and playback, depending on the sample rates defined by the customer's software. INPUT SAMPLE RATE TO DURATION INPUT SAMPLE Rate (kHz) 8.0 6.4 5.3 4.0 Duration1 (Minutes) 8 min 3 sec 10 min 4 sec 12 min 9 sec 16 min 6 sec Typical Filter Pass Band (kHz) 3.7 2.9 2.5 1.8 1. Minus any pages selected for digital storage -8 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY FLASH STORAGE One of the benefits of Winbond's ChipCorder technology is the use of on-chip nonvolatile memory, which provides zero-power message storage. A message is retained for up to 100 years (typically) without power. In addition, the device can be re-recorded over 10,000 times (typically) for digital messages and over 100,000 times (typically) for analog messages. A new feature has been added that allows for the allocation of memory space in the I5216, to either digital or analog storage, when recording. When making a recording, if a section is assigned for digital or analog data storage, the system microcontroller stores this information in the Message Address Table. MICROCONTROLLER INTERFACE The I5216 is controlled through an I C 2-wire interface. This synchronous serial port allows commands, configurations, address data, and digital data to be loaded to the device, while allowing status, digital data and current address information to be read back from the device. In addition to the serial interface, two other pins can be connected to the microcontroller for enhanced interface: the RAC timing pin and the INT\ pin for interrupts to the controller. Communications with all of the internal registers is through the serial bus, as well as digital memory Read and Write operations. 2 PROGRAMMING The I5216 series is also ideal for playback-only applications, whereas single or multiple messages may 2 be played back when desired. Playback is controlled through the I C port. Once the desired message configuration is created, duplicates can easily be generated via a Winbond or third-party programmer. For more information on available application tools and programmers, please see the Winbond web site at http://www.winbond-usa.com/. APPLICATIONS The I5216 is a single chip solution for voice and analog storage that also includes the capability to store digital information in the memory array. The array may be divided between analog and digital storage, as the user chooses, when configuring the device. Looking at the block diagram on the following page, one can see that the I5216 may be very easily designed into a cellular phone. Placing the device between the microphone and the existing baseband chip takes care of the transmit path. The SDI/SDIO of the baseband chip is connected to the SDIO/SDI 2 of the I5216. Two pins are needed for the I C digital control and digital information for storage. -9 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY INT SCL SDA Starting at the MICROPHONE inputs, the input signal at the MICROPHONE inputs can be routed in the following ways: * * * * directly through the Voice band CODEC of the I5216 chip, then through the SDIO pin, to output the digital PCM signal. through the AGC amplifier, before it is routed to the voice band CODEC. through the AGC amplifier to the storage array through the AGC amplifier and mixed with an analog voice band CODEC signal coming from the digital SDI pin In addition, if the phone is inserted into a "hands-free" car kit, then the signal from the pickup microphone in the car can be passed through to the same places from the AUX IN pin and the phone's microphone is switched off. In this scenario, the other party's voice from the phone would be played into the PCM IN input and passed through to the AUX OUT pin that would drive the car kit's loudspeaker. Depending upon whether one desires recording one side (simplex) or both sides (duplex) of a conversation, the various paths will also be switched through to the low pass filter (for antialiasing) and into the storage array. Later, the cell phone owner can play back the messages from the array. When this happens, the Array Output MUX is connected to the volume control, through the Output MUX, to the Speaker Amplifier. For applications other than a cell phone, the audio paths can be switched into many different and flexible configurations. Some examples follow. -10 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY TRANSFORMER APPLICATION To Microcontroller I2C interface and Address setting .1F Vcc .1F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCCD SCL A1 SDA A0 VSSD 28 27 MCLK 26 VCCD INT RAC 25 4.7K 4.7K 1.5k .1F SDIO 24 SDI Electret Microphone WM-54B Panasonic .1F 1.5k 23 VSSD ISD521 VSSA 22 VSSA WS 21 MIC+ SCK 20 MICNC 19 18 MICBS AUX OUT ACAP AUX IN 17 16 VCCA SP15 VSSA SP+ 13.824 MHz Vcc Vcc PCM OUT PCM IN 8 KHz 2.048 MHz TO AUXILIARY INPUT .1F .1F 1F 600 PDIP N=1 TIP N=1 RING 600 -11 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY HANDSET APPLICATION To Microcontroller I2C interface and Address setting .1F Vcc .1F 1.5k .1F 1 2 3 4 5 6 7 8 9 VCCD SCL A1 SDA A0 VSSD VSSD VSSA MIC+ MICMICBS ACAP SP VSSA VCCD 28 4.7K 4.7K 13.824 MHz Vcc Vcc PCM OUT PCM IN 8 KHz 2.048 MHz TO RINGER AUXILIARY INPUT .1F MCLK 27 26 RAC 25 SDIO 24 23 SDI INT ISD521 VSSA Electret Microphone WM-54B Panasonic .1F 1.5k .1F 10 11 12 13 14 22 21 20 SCK 19 WS NC AUX OUT 18 AUX IN 17 VCCA 16 SP+ 15 PDIP RECEIVE -12 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY CAR STEREO APPLICATION To Microcontroller I2C interface and Address setting .1F Vcc .1F 1 2 3 4 5 6 VCCD SCL A1 SDA A0 VSSD VSSD VSSA MIC+ MICMICBS ACAP SPVSSA VCCD 28 MCLK 27 1.5k .1F SDI 26 RAC 25 24 SDIO 23 INT 4.7K 4.7K 20.48 MHz Vcc Vcc I2S SERIAL I/O 7 8 9 10 11 12 13 14 1F ISD521 VSSA WS SCK NC Electret Microphone WM-54B Panasonic .1F 1.5k AUX OUT AUX IN VCCA SP+ 22 21 20 19 18 17 16 15 48 KHz 3.072 MHz .1F PDIP -13 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY INTERNAL REGISTERS The following tables provide a general illustration of the bits. There are three configuration registers: CFG0, CFG1 and CFG2. Thus, there are six 8-bit bytes to be loaded during the set-up of the device. CFG0 Bit no. D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 (MSB) Signal VLPD OPA0 OPA1 OPS0 OPS1 CDI0 CDI1 AMT0 OSPD INS0 AXPD AXG0 AXG1 CIG0 CIG1 CIG2 Description Power down the Volume Control. Power down Speaker driver and/or Auxiliary output. Power down Speaker driver and/or Auxiliary output. Select speaker output multiplexer. Select speaker output multiplexer. Analog to digital converter input selector. Analog to digital converter input selector. Compress the filter signal. Power down the internal ChipCorder oscillator. Select Microphone input or Auxiliary input. Power down Auxiliary input amplifier. Auxiliary input amplifier gain setting. Auxiliary input amplifier gain setting. Input gain setting for the Analog to digital converter. Input gain setting for the Analog to digital converter. Input gain setting for the Analog to digital converter. -14 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY CFG1 Bit no. D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 (MSB) Signal AGPD FLPD FLD0 FLD1 FLS0 S2M0 S2M1 S1M0 S1M1 S1S0 S1S1 VOL0 VOL1 VOL2 VLS0 VLS1 Description Power down the Microphone AGC Power down the Filter Set the duration and sample rate of the ChipCorder Set the duration and sample rate of the ChipCorder Select the filter input signal Select Sum Amplifier 2 input Select Sum Amplifier 2 input Select Sum Amplifier 1 input Select Sum Amplifier 1 input Select Sum Amplifier 1 multiplexer Select Sum Amplifier 1 multiplexer Volume Control Setting Volume Control Setting Volume Control Setting Select Volume Control input Select Volume Control input -15 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY CFG2 Bit no. D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 (MSB) Signal ADPD DAPD LAW0 LAW1 I2S0 HSR0 HPF0 MUTE CKDV COG0 COG1 COG2 CKD2 Description Power down the Analog to Digital converter Power down the Digital to Analog converter Select digital -Law or A-Law input/output format Select digital -Law or A-Law input/output format Select the I2S interface Enable the high sample rate mode Enable High Pass Filter Mute the CODEC A/D and D/A path Divide MCLK by 2560 or 1728 for 8 kHz ChipCorder sample rate Output gain setting for the Digital to Analog converter Output gain setting for the Digital to Analog converter Output gain setting for the Digital to Analog converter Divide MCLK frequency by 2 or 1 Reserved Reserved Reserved -16 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY MEMORY ORGANIZATION The I5216 memory array is arranged as 1888 rows (or pages) of 2048 bits, for a total memory of 3,866,624 bits. The primary addressing for the 2048 pages is handled by 11 bits of address data in the analog mode. At the 8 kHz sample rate, each page contains 256 milliseconds of audio. Thus, at 8 kHz there is actually room for 8 minutes and 3 seconds of audio. A memory page is 2048 bits organized as thirty-two 64-bit "blocks" when used for digital storage. The contents of a page are either analog or digital. This is determined by instruction (op code) at the time the data is written. A record of what is analog and what is digital, and where, is stored by the system microcontroller in the message address table (MAT). The MAT is a table kept in the microcontroller memory that defines the status of each message "block." It can be stored back into the I5216 if the power fails or the system is turned off. Use of this table allows for efficient message management. Segments of messages can be stored wherever there is available space in the memory array. [This is explained in detail for the Winbond I5008 in Applications Note #No.9 and will similarly be in a later Note for the I5216.] When a page is used for analog storage, the same 32 blocks are present, but there are 8 EOM (Endof-Message) markers. This means that for each 4 blocks there is an EOM marker at the end. Thus, when recording, the analog recording will stop at any one of eight positions. At 8 kHz, this results in a resolution of 32 msec when ENDING an analog recording. Beginning an analog recording is limited to the 256 msec resolution provided by the 11-bit address. A recording does not immediately stop when the Stop command is issued, but continues until the 32-millisecond block is filled. Then a bit is placed into the EOM memory to develop the interrupt that signals a message is finished playing in the Playback mode. Digital data is sent and received, serially, over the I C interface. The data is serial-to-parallel converted and stored in one of two alternating (commutating) 64-bit shift registers. When an input register is full, it becomes the register that is parallel written into the array. The prior write register becomes the new serial input register. A mechanism is built in to ensure there is always a register available for storing new data. Storing data in the memory is accomplished by accepting data, one byte at a time, and issuing an acknowledgement. If data is coming in faster than it can be written, then the chip will not issue an acknowledgement to the host microcontroller until it is ready. The read mode is the opposite of the write mode. Data is read into one of two 64-bit registers from the 2 array and serially sent to the I C port. (See Digital Mode on page 41 for details). 2 OPERATION MODES DESCRIPTION I C PORT Important note: The content contained herein of the rest of this datasheet assumes that the 2 2 reader is familiar with the I C serial interface. Additional information on I C may be found in 2 the I C section of this document. If you are not familiar with this serial protocol, please read the I2C section to familiarize yourself with it. A significant amount of additional information on 2 I C can also be found on the Philips web page at http://www.philips.com/. 2 -17 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I2C SLAVE ADDRESS The I5216 has a 7 bit slave address of <100 00xy> where x and y are equal to the state, respectively, of the external address pins A1 and A0. Because all data bytes are required to be 8 bits, the LSB of the address byte is the Read/Write selection bit that tells the slave whether to transmit or receive data. Therefore, there are eight possible slave addresses for the I5216 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Slave Address <100 00 00> <100 00 01> <100 00 10> <100 00 11> <100 00 00> <100 00 01> <100 00 10> <100 00 11> R/W\ Bit 0 0 0 0 1 1 1 1 HEX Value 80 82 84 86 81 83 85 87 2 To use more than four I5216 devices in an application requires some external switching of the I C link. -18 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I2C OPERATION DEFINTIONS There are many control functions used to operate the I5216. Among them are the following. Conventions used in I C Data Transfer Diagrams 2 READ STATUS COMMAND: The read status command is a read request from the Host processor to the I5216 without delivering a Command Byte. The Host supplies all of the clocks (SCL). In each case, the entity sending the data drives the data line (SDA). The Read 2 Status Command is executed by the following I C sequence. 1. Host executes I C START 2. Send Slave Address with R/W bit = "1" (Read) 81h. 3. Slave responds back to Host an Acknowledge (ACK), followed by 8 bit Status word. 4. Host sends an Acknowledge (ACK) to Slave. 5. Wait for SCL to go HIGH. 6. Slave responds with Upper Address byte of internal address register. 7. Host sends an ACK to Slave. 8. 9. 2 S P = START Condition = STOP Condition DATA = 8 bit data transfer R W A N = "1" in the R/W bit = "0" in the R/W bit = ACK (Acknowledge) = No ACK = 7 bit Slave Address Wait for SCL to go high. Slave responds with Lower Address byte of internal address register. 2 SLAVE ADDRESS 10. Host sends a NO ACK to Slave, then executes I C STOP The Box color indicates the direction of data flow = Host to Slave (Gray) = Slave to Host (White) Note: The processor could have sent an I C STOP after the Status Word data transfer, and thus aborted the transfer of the Address bytes A graphical representation of this operation is found below. See the caption box above for more explanation. S SLAVE ADDRESS R A DATA A DATA A DATA N P 2 Status High Addr. Low Addr. -19 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY LOAD COMMAND BYTE REGISTER (Single Byte Load) A single byte may be written to the Command Byte Register in order to power up the device, start or stop Analog Record (if no address information is needed), or perform a Message Cueing function. The Command Byte Register is loaded as follows: 1. 2. 3. 4. 5. 6. 7. 8. Host executes I C START. Send Slave Address with R/W bit = "0" (Write) [80h]. Slave responds back with an ACK. Wait for SCL to go HIGH. Host sends a command byte to Slave. Slave responds with an ACK. Wait for SCL to go HIGH. Host executes I C STOP. 2 2 S SLAVE ADDRESS W A DATA A Command Byte LOAD COMMAND BYTE REGISTER (Address Load): For the normal addressed mode the Registers are loaded as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Host executes I C START. Send Slave Address with R/W bit = "0" (Write). Slave responds back with an ACK. Wait for SCL to go HIGH. Host sends a byte to Slave - (Command Byte). Slave responds with an ACK. Wait for SCL to go HIGH. Host sends a byte to Slave - (High Address Byte). Slave responds with an ACK. 2 10. Wait for SCL to go HIGH. 11. Host sends a byte to Slave - (Low Address Byte). 12. Slave responds with an ACK. 13. Wait for SCL to go HIGH. 14. Host executes I C STOP. S SLAVE ADDRESS W A DATA A DATA A DATA A P 2 Command High Addr. Low Addr. -20 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I2C CONTROL REGISTERS The I5216 is controlled by loading commands to, or reading commands from the internal command, configuration and address registers. The Command byte sent is used to start and stop recording, write or read digital data and perform other functions necessary for the operation of the device. COMMAND BYTE Control of the I5216 is implemented through an 8-bit command byte that is sent after the 7-bit device address and the 1-bit Read/Write selection bit. The 8 bits are: Global power up bit DAB bit: determines whether device is performing an analog or digital function 3 function bits: these determine which function the device is to perform in conjunction with the DAB bit. 3 register address bits: these determine if and when data is to be loaded to a register Power Up Bit C7 PU C6 DAB C5 FN2 C4 FN1 C3 FN0 C2 RG2 C1 RG1 C0 RG0 Function Bits Register Bits FUNCTION BITS The command byte function bits are detailed in the table to the right. C6, the DAB bit, determines whether the device is performing an analog or digital function. The other bits are decoded to produce the individual commands. Note that not all decode combinations are currently used; they are reserved for future use. Out of 16 possible codes, the I5216 uses 7 for normal operation. The other 9 are No Ops. Command Bits C6 DAB 0 0 0 0 1 1 1 C5 FN2 0 1 0 1 1 0 0 C4 FN1 0 0 1 1 0 0 1 C3 FN0 0 1 0 1 0 1 0 Function STOP (or do nothing) Analog Play Analog Record Analog MC Digital Read Digital Write Erase (row) -21 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY REGISTER BITS The register load may be used to modify a command sequence (such as load an address) or used with the null command sequence to load a configuration or test register. Not all registers are accessible to the user. [The remaining three codes are No Ops.] RG2 C2 0 0 0 0 1 RG1 C1 0 0 1 1 0 RG0 C0 0 1 0 1 1 No action Load Address Load CFG0 Load CFG1 Load CFG2 Function OPCODE SUMMARY OpCode Command Description The following commands are used to access the chip through the I C port: Play: analog play command. Record: analog record command. Message Cue: analog message cue command. Enter Digital mode. Read: digital read command. Write: digital write command. Erase: digital page and block erase command. Exit Digital mode. Power up: global power up/down bit. (C7). Load address: load address register (is incorporated in play, record, read and write commands). Load CFG0: load configuration register 0. Load CFG1: load configuration register 1. Load CFG2: load configuration register 2. Read STATUS: Read the interrupt status and address register, including a hardwired device ID. 2 -22 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY OPCODE COMMAND BYTE TABLE Pwr OPCODE COMMAND BIT NUMBER HEX CMD PU C7 DAB C6 Function Bits FN2 C5 FN1 C4 FN0 C3 Register Bits RG2 C2 RG1 C1 RG0 C0 POWER UP POWER DOWN STOP (DO NOTHING) STAY ON STOP (DO NOTHING) STAY OFF 80 00 80 00 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOAD ADDRESS LOAD CFG0 LOAD CFG1 LOAD CFG2 81 82 83 85 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 RECORD ANALOG RECORD ANALOG @ ADDR PLAY ANALOG PLAY ANALOG @ ADDR MSG CUE ANALOG MSG CUE ANALOG @ ADDR ENTER DIGITAL MODE ERASE DIGITAL PAGE WRITE DIGITAL WRITE DIGITAL @ ADDR READ DIGITAL READ DIGITAL @ ADDR EXIT DIGITAL MODE READ STATUS REGISTER 1 90 91 A8 A9 B8 B9 C0 D1 C8 C9 E0 E1 40 N/A 1 1 1 1 1 1 1 1 1 1 1 1 0 N/A 0 0 0 0 0 0 1 1 1 1 1 1 1 N/A 0 0 1 1 1 1 0 0 0 0 1 1 0 N/A 1 1 0 0 1 1 0 1 0 0 0 0 0 N/A 0 0 1 1 1 1 0 0 1 1 0 0 0 N/A 0 0 0 0 0 0 0 0 0 0 0 0 0 N/A 0 0 0 0 0 0 0 0 0 0 0 0 0 N/A 0 1 0 1 0 1 0 1 0 1 0 1 0 N/A -23 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY 1 See Playback and Stop Cycle on page 62 for details. DATABYTES In the I C write mode, the device can accept data sent after the command byte. If a register load option is selected, the next two bytes are loaded into the selected register. The format of the data is MSB first, 2 as specified by the I C standard. Thus to load DATA<15:0> into the device, DATA<15:8> is sent first, the byte is acknowledged, and DATA<7:0> is sent next. The address register consists of two bytes. The format of the address is as follows: ADDRESS<15:0> = PAGE_ADDRESS<10:0>, BLOCK_ADDRESS<4:0> If an analog function is selected, the block address bits must be set to 00000. Digital Read and Write are block addressable. When the device is polled with the Read Status command, it will return three bytes of data. The first byte is the status byte, the next is the upper address byte and the last is the lower address byte. The status register is one byte long and its bit function is: STATUS<7:0> = EOM, OVF, READY, PD, PRB, DEVICE_ID<2:0> The lower address byte will always return the block address bits as zero, either in digital or analog mode. The functions of the bits are: BIT# 7 6 5 4 3 2 1 0 DEVICE_ID An internal device ID. This is 001 for the I5216. NAME EOM OVF READY PD PRB FUNCTION Indicates whether an EOM interrupt has occurred. Indicates whether an overflow interrupt has occurred. Indicates the internal status of the device - if READY is LOW no new commands should be sent to device. Device is powered down if PD is HIGH. Play/Record mode indicator. HIGH=Play/LOW=Record. 2 It is good practice to read the status register after a Write or Record operation to ensure that the device is ready to accept new commands. Depending upon the design and the number of pins available on the controller, the polling overhead can be reduced. If INT\ and RAC are tied to the microcontroller, the controller does not have to poll as frequently to determine the status of the I5216 -24 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY POWER-UP SEQUENCE This sequence prepares the I5216 for an operation to follow, and waits for the Tpud time before sending the next command sequence. 1. Send I C Start. 2. Send one byte 10000000 {Slave Address, R/W = 0} 80h. 3. Slave ACK. 4. Wait for SCL High. 5. Send one byte 10000000 {Command Byte = Power Up} 80h. 6. Slave ACK. 7. Wait for SCL High. 8. Send I C Stop. 2 2 SET MASTER CLOCK DIVISION RATIO The I5216 product has two Master Clock configuration bits that allow four possible Master Clock frequencies. The Master Clock Division ratios can be set by bits CKD2 and CKDV. These are bits D12 and D8 of CFG2, respectively. The combination of these bits, with the sample rate bit HSR0, also sets the CODEC sample frequency. Master Clock Possible Settings FMCLK 13.824 MHz 20.48 MHz 27.648 MHz 40.96 MHz 13.824 MHz 20.48 MHz 27.648 MHz 40.96 MHz *not tested HSR0 (D5) (CFG2) 0 0 0 0 1 1 1 1 CKD2 (D12) (CFG2) 0 0 1 1 0 0 1 1 CKDV (D8) (CFG2) 0 1 0 1 0 1 0 1 FSCODEC 8 kHz 11.852 kHz* 8 kHz 11.852 kHz* 32 kHz* 44.1 - 48 kHz 32 kHz* 44.1-48 kHz -25 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY PLAYBACK MODE The command sequence for an analog Playback operation can be handled several ways. One technique is to do a Load Address (81h), which requires sending a total of four bytes, followed by a Play Analog, which is a Command Byte (A8h) preceded by the Slave Address Byte. This is a total of six bytes plus the times for Start, ACK, and Stop. Another approach for an analog Playback operation is via a single four byte exchange, which consists of the Slave Address (80h), the Command Byte (A9h) for Play Analog @ Address, and the two address bytes. RECORD MODE The command sequence for an Analog Record is a four byte sequence consisting of the Slave Address (80h), the Command Byte (91h) for Record Analog @ Address, and the two address bytes. 2 (See I C Interface on page 17 for more detail.) FEED THROUGH MODE SDI PCM Interface /A-Law Expander 2 FILTO+ VOL+ SUM2+ DAO+ SPEAKER Spkr. AMP AMP Output DAC 3 3 Output GAIN SP+ SP- DAOSUM2VOLFILTO- MUX WS SCK (LAW1,LAW0) (DAPD,HSR0,MUTE) (COG2,COG1,COG0) (OPA1,O PA0) 2 (OPS1,O PS0) 2 CODEC In Mux SDIO 1 /A-Law Compressor 2 SUM2+ INP+ ADC 4 Input GAIN MIC+ MIC INPSUM2- (I2S0) (LAW1,LAW0) (ADPD,HSR0,HPF0,MUTE) 3 (CIG2,CIG1,CIG0) (CDI1,CDI0) 2 This diagram shows the part of the I5216 block diagram that is used in Feed Through Mode. The rest of the chip will be powered down to conserve power. Note that the Microphone and Speaker +/- paths are differential - 26 - Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY FEED THROUGH MODE The previous examples were dependent upon the device already being powered up and the various paths being set through the device for the desired operation. To set up the device for the various paths requires loading the three 16-bit Configuration Registers with the correct data. For example, in the Feed Through Mode, the device only needs to be powered up and a few paths selected. This mode enables the I5216 to connect to a cellular or cordless baseband phone chip set without affecting the audio source or destination. There are two paths involved: the transmit path and the receive path. The transmit path connects the Winbond chip's microphone source through to the digital audio input on the baseband chip set. The receive path connects the baseband chip set's digital output through to the speaker driver on the Winbond chip. This allows the Winbond chip to substitute for Analog to Digital and Digital to Analog conversion, and incidentally gain access to the audio, both to and from the baseband chip set. To setup the environment described above, a series of commands need to be sent to the I5216. First, the chip needs to be powered up as described in Power-Up Sequence on page 25. Then the Configuration Registers need to be filled with the specific data to connect the desired paths. In the case of the Feed Through Mode, most of the chip can remain powered down. The Feed Through Mode diagram illustrates the affected paths To select the Feed Through mode, the following control bits must be configured in the I5216 configuration register To set up the transmit path: 1. Select the FTHRU path through the CODEC INPUT MUX--Bits CDI1 and CDI0 control the state of the CODEC INPUT MUX. These are the D6 and D5 bits, respectively, of Configuration Register 0 (CFG0) and they should be set to ONE and ZERO, respectively, to select the FTHRU path. 2. Power up the ADC--Bit ADPD controls the power up state of ADC. This is bit D0 of CFG2 and it should be a ZERO to power up the ADC. 3. Set the CODEC input gain. The input gain setting will depend on the input level at the MIC+/pins and can be set by the CODEC INPUT GAIN Bits CIG2, CIG1 and CIG0. These are the D15, D14 and D13 bits, respectively, of Configuration Register 0 (CFG0). The input gain can be set according to the following table. (Table A) 4. Enable the High Pass Filter, if desired, in the low sample rate mode. This can be done by setting bit HPF0 to ONE. This is bit D6 of CFG2. 5. Select the low or high sample rate mode by setting bit HSR0. This is bit D5 of CFG2. HSR0 needs to be set to ONE for the high sample rate mode. 6. Set the MUTE bit if desired. This bit can be set temporarily to reduce power up `pops' or to set the system on hold. This bit is D7 of CFG2 and needs to be set to ONE in order to mute the signal. 7. Set the digital data format through bits LAW1 and LAW0. These are bits D3 and D2 of CFG2, respectively. The data format can be chosen according to the following table. (Table B). 8. Set the interface mode to PCM-interface by setting bit I S0 to ZERO. This will also enable full duplex mode. This bit is bit D4 of CFG2. 9. Set the Master Clock division ratios as described in Set Master Clock Division Ratio on page 25. 2 - 27 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY Table A CIG2 0 0 0 0 1 1 1 1 CIG1 0 0 1 1 0 0 1 1 CIG0 0 1 0 1 0 1 0 1 GAIN 0.80 1.00 1.20 1.25 1.40 1.60 1.80 2.00 1 0 LAW 1 Table B LAW 0 0 Data format Two's complement 0 1 A-Law -Law 1 0 1 Table C HSRO 0 1 Sample Rate Mode Low High HPF0 0 1 Table D High Pass Filter Bypassed Enabled Table E ADPD 0 1 CODEC ADC Power Up Power Down DAPD 0 1 Table F CODEC DAC Power Up Power Down Table G I S0 0 1 2 Table H MUTE 0 1 CONDITION Power Up Mute CODEC ADC & DAC CONDITION PCM Interface I S Interface 2 - 28 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY To set up the receive path: Set up the CODEC output gain amplifier for the correct gain--Bits COG0, COG1 and COG2 control the gain settings of this amplifier. These are bits D9, D10 and D11, respectively, of CFG2. The table below will help determine the setting COG2 0 0 0 0 1 1 1 1 COG1 0 0 1 1 0 0 1 1 COG0 0 1 0 1 0 1 0 1 GAIN (dB) 0 +2 +4 +6 -8 -6 -4 -2 1. Power up the DAC--Bit DAPD controls the power up state of the DAC. This is bit D1 of CFG2 and should be a ZERO to power up the DAC. 2. Select the DAC path through the OUTPUT MUX--Bits OPS0 and OPS1 control the state of the OUTPUT MUX. These are bits D3 and D4, respectively, of CFG0 and they should be set to the state where D3 is ONE and D4 is ZERO to select the DAC path. 3. Power up the Speaker Amplifier--Bits OPA0 and OPA1 control the state of the Speaker and AUX amplifiers. These are bits D1 and D2, respectively, of CFG0. They should be set to the state where D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and configures it for a higher gain setting (for use with a piezo speaker element) and also powers down the AUX output stage. 4. Set the Master Clock configuration bits and bits HSR0, MUTE, HPF0, I S0, LAW1 and LAW0 as described in the previous sections. The status of the rest of the functions in the I5216 chip must be defined before the configuration registers settings are updated: 1. Power down the Volume Control Element--Bit VLPD controls the power up state of the Volume Control. This is bit D0 of CFG0 and it should be set to a ONE to power down this stage. 2. Power down the internal oscillator--Bit PDOS controls the power up state of the internal ChipCorder oscillator. This is bit D8 of CFG0 and it should be set to a ONE to power down this oscillator 2 - 29 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY 3. Power down the AUX IN amplifier--Bit AXPD controls the power up state of the AUX IN input amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this stage. 4. Power down the SUM1 and SUM2 Mixer amplifiers--Bits S1M0 and S1M1 control the SUM1 mixer and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1, and bits D5 and D6 in CFG1, respectively. All four bits should be set to a ONE in order to power down these two amplifiers. 5. Power down the FILTER stage--Bit FLPD controls the power up state of the FILTER stage in the device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage. 6. Power down the AGC amplifier--Bit AGPD controls the power up state of the AGC amplifier. This is bit D0 in CFG1 and should be set to a ONE to power down this stage. 7. Don't Care bits--All other bits are not used in Feed Through Mode. Their bits may be set to either level. In this example, we will set all the "Don't Care" bits to a ZERO. The following example shows the setup for a full-duplex feed-through path at 8 kHz sampling rate. The twos complement data format is enabled. The High Pass filter is also enabled. The Master Clock input is running at 13.824MHz. CFG0=0010 0101 0100 1011 (hex 254B) and CFG1=0000 0001 1110 0011 (hex 01E3). and CFG2=0000 0000 0100 0000 (hex 0040). Since three registers are being loaded, CFG0 is loaded, followed by the loading of CFG1 and CFG2. These three registers must be loaded in this order. The internal set up for these registers will take effect synchronously, with the rising edge of SCL. CALL RECORD The call record mode adds the ability to record the incoming phone call. In most applications, the I5216 would first be set up for Feed Through Mode as described above. When the user wishes to record the incoming call, the set up of the chip is modified to add that ability. For the purpose of this explanation, we will use the 6.4 kHz ChipCorder sample rate during recording. The block diagram of the I5216 shows that the Multilevel Storage array is always driven from the SUM2 SUMMING amplifier. The path traces back from there, through the LOW PASS Filter, the FILTER MUX, the SUM1 SUMMING amplifier, the SUM1 MUX, back to the origin CODEC. Feed Through Mode has already powered up the CODEC, so we only need to power up and enable the path to the Multilevel Storage array from that point: - 30 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY 1. Select the CODEC path through the SUM1 MUX--Bits S1S0 and S1S1 control the state of the SUM1 MUX. These are bits D9 and D10, respectively, of CFG1 and they should be set to the state where both D9 and D10 are ZERO to select the CODEC path. 2. Select the SUM1 MUX input (only) to the S1 SUMMING amplifier--Bits S1M0 and S1M1 control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8, respectively, of CFG1 and they should be set to the state where D7 is ONE and D8 is ZERO to select the SUM1 MUX (only) path. 3. Select the SUM1 SUMMING amplifier path through the FILTER MUX--Bit FLS0 controls the state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path. 4. Deselect the signal compression-Bit AMT0 controls the signal compression. This is bit D7 of CFG0 and it must be set to ZERO. 5. Power up the LOW PASS FILTER--Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 6. Select the 6.4 kHz sample rate--Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 6.4 kHz sample rate, D2 must be set to ONE and D3 set to ZERO. 7. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier--Bits S2M0 and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6, respectively, of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. The configuration settings in the call record mode are: CFG0=0100 0100 0000 1011 (hex 440B). CFG1=0000 0000 1100 0101 (hex 00C5). CFG2=0000 0000 0100 0000 (hex 0040). MEMO RECORD The Memo Record mode sets the chip up to record from the local microphone into the chip's Multilevel Storage Array. A connected cellular telephone or cordless phone chip set may remain powered down since they are not active in this mode. The path to be used is microphone input to AGC amplifier, then through to the INPUT SOURCE MUX, to the SUM1 SUMMING amplifier. From there, the path goes through the FILTER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the MULTILEVEL STORAGE ARRAY. In this example, we will select the 5.3 kHz sample rate. The rest of the chip may be powered down. 1. Power up the AGC amplifier Bit AGPD controls the power up state of the AGC amplifier. This is bit D0 of CFG1 and must be set to ZERO to power up this stage. 2. Select the AGC amplifier through the INPUT SOURCE MUX--Bit INS0 controls the state of the INPUT SOURCE MUX. This is bit D9 of CFG0 and must be set to a ZERO to select the AGC amplifier. Publication Release Date: November 30, 2001 Revision A1 - 31 I5216 SERIES Advanced Information PRELIMINARY 3. Select the INPUT SOURCE MUX (only) to the S1 SUMMING amplifier--Bits S1M0 and S1M1 control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8, respectively, of CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the INPUT SOURCE MUX (only) path. 4. Select the SUM1 SUMMING amplifier path through the FILTER MUX--Bit FLS0 controls the state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path. 5. Deselect the signal compression-Bit AMT0 controls the signal compression. This is bit D7 of CFG0 and it must be set to ZERO. 6. Power up the LOW PASS FILTER--Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 7. Select the 5.3 kHz sample rate--Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE. 8. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier - BITS S2M0 and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6, respectively, of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. 9. Power up the Internal Oscillator--Bit OSPD controls the power up state of the Internal Oscillator. This is bit D8 of CFG0 and it must be set to ZERO to power up the Internal Oscillator. To set up the chip for Memo Record, the configuration registers are set up as follows: CFG0=0000 0100 0000 0001 (hex 0401). CFG1=0000 0001 0100 1000 (hex 0148). CFG2=0000 0000 0000 0011 (hex 0003). Only those portions necessary for this mode are powered up. MEMO AND CALL PLAYBACK This mode sets the chip up for local playback of messages that were recorded earlier. The playback path is from the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage. From there, the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX, through the VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are driving a piezo speaker element and that this audio was previously recorded at 8 kHz. All unnecessary stages will be powered down. 1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX--Bit FLS0, the state of the FILTER MUX. This is bit D4 of CFG1 and must be set to ONE to select the MULTILEVEL STORAGE ARRAY. - 32 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY 2. Power up the LOW PASS FILTER--Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 3. Select the 8.0 kHz sample rate--Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO. 4. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier --Bits S2M0 and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6, respectively, of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. 5. Select the SUM2 SUMMING amplifier path through the VOLUME MUX--Bits VLS0 and VLS1 control the VOLUME MUX stage. These bits are D14 and D15, respectively, of CFG1. They should be set to the state where D14 is ONE and D15 is ZERO to select the SUM2 SUMMING amplifier. 6. Power up the VOLUME CONTROL LEVEL--Bit VLPD controls the power-up state of the VOLUME CONTROL attenuator. This is Bit D0 of CFG0. This bit must be set to a ZERO to power-up the VOLUME CONTROL. 7. Select a VOLUME CONTROL LEVEL--Bits VOL0, VOL1 and VOL2 control the state of the VOLUME CONTROL LEVEL. These are bits D11, D12, and D13, respectively, of CFG1. A binary count of 000 through 111 controls the amount of attenuation through that stage. In most cases, the software will select an attenuation level according to the desires of the product user. In this example, we will assume the user wants an attenuation of -12 dB. For that setting, D11 should be set to ONE, D12 should be set to ONE, and D13 should be set to a ZERO. 8. Select the VOLUME CONTROL path through the OUTPUT MUX--These are bits D3 and D4, respectively, of CFG0. They should be set to the state where D3 is ZERO and D4 is a ZERO to select the VOLUME CONTROL. 9. Power up the SPEAKER amplifier and select the HIGH GAIN mode--Bits OPA0 and OPA1 control the state of the speaker (SP+ and SP-) and AUX OUT outputs. These are bits D1 and D2 of CFG0. They must be set to the state where D1 is ONE and D2 is ZERO to power-up the speaker outputs in the HIGH GAIN mode and to power-down the AUX OUT. 10. Power up the Internal Oscillator--Bit OSPD controls the power up state of the Internal Oscillator. This is bit D8 of CFG0 and it must be set to ZERO to power up the Internal Oscillator. To set up the chip for Memo or Call Playback, the configuration registers are set up as follows: CFG0=0010 0100 0010 0010 (hex 2422). CFG1=0101 1001 1101 0001 (hex 59D1). CFG2=0000 0000 0000 0011 (hex 0003). Only those portions necessary for this mode are powered up. - 33 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY MESSAGE CUEING Message cueing allows the user to skip through messages, without having to know the actual physical location of each message. This operation is used during playback. In this mode, the messages are skipped 512 times faster than in normal playback mode. This operation will stop when an EOM marker is reached. Then, the internal address counter will be pointing to the next message. ANALOG MODE AUX IN DESCRIPTION The AUX IN is an additional audio input to the Winbond I5216, such as from the microphone circuit in a mobile phone "car kit." This input has a nominal 700 mV p-p level at its minimum gain setting (0 dB). (See Aux In Amplifier Gain Settings table on page 50.) Additional gain is available in 3 dB steps 2 (controlled by the I C serial interface) up to 9 dB. INTERNAL TO THE DEVICE Rb CCOUP=0.1 F Ra AUX IN Input AUX IN Input Amplifier NOTE: fCUTOFF= 1 2RaCCOUP - 34 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I5216 ANALOG STRUCTURE (Left Half) DESCRIPTION INP AGC AMP INP SUM1 MUX 2 SUM1 Summing AMP SUM1 Input Source MUX 1 AUX IN ( S1M0 ) S1M1 FILTO SUM1 MUX (INS0) ARRAY DAC OUT S1M1 0 0 1 1 S1M0 0 1 0 1 SOURCE BOTH SUM1 MUX ONLY INP Only POWER DOWN 2 ( S1S0 ) S1S1 S1S1 INSO 0 1 SOURCE AGC AMP AUX IN AMP 0 0 1 1 S1S0 0 1 0 1 SOURCE DAC OUT (DAO) ARRAY FILTO N?C CIG2 15 VLS1 15 X CIG1 14 VLS0 14 X CIG0 13 VOL2 13 X AXG1 12 VOL1 12 CKD2 AXG0 11 VOL0 11 COG2 AXPD 10 S1S1 10 COG1 INS0 9 S1S0 9 COG0 OSPD 8 S1M1 8 CKDV AMT0 7 S1M0 7 MUTE CDI1 6 S2M1 6 HPF0 CDI0 5 S2M0 5 HSR0 OPS1 4 FLS0 4 I2S0 OPS0 3 FLD1 3 LAW1 OPA1 2 FLD0 2 LAW0 OPA0 1 FLPD 1 DAPD VLPD 0 AGPD 0 ADPD CFG0 CFG1 CFG2 - 35 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I5216 ANALOG STRUCTURE (Right Half) DESCRIPTION FLPD 0 1 CONDITION Power Up Power Down S2M1 0 0 1 1 S2M0 0 1 0 1 SOURCE BOTH AUX IN ONLY FILTO ONLY Power Down FLD1 0 0 1 1 FLD0 0 1 0 1 SAMPLE RATE 8 KHz 6.4 KHz 5.3 KHz 4.0 KHz FILTER PASS BAND 3.7 KHz 2.9 KHz 2.5 KHz 1.8 KHz FLS0 0 1 SOURCE SUM1 ARRAY AMT0 0 1 Signal Output Uncompressed Compressed OSPD 0 1 Condition Power Up Internal Oscillator Power Down Internal Oscillator CKD2 0 1 Condition Divide Master Clock frequency by 1 Divide Master Clock frequency by 2 CKDV 0 1 Condition Divide Master Clock frequency by 1728 Divide Master Clock frequency by 2560 CIG2 15 VLS1 15 X CIG1 14 VLS0 14 X CIG0 13 VOL2 13 X AXG1 12 VOL1 12 CKD2 AXG0 11 VOL0 11 COG2 AXPD 10 S1S1 10 COG1 INS0 9 S1S0 9 COG0 OSPD 8 S1M1 8 CKDV AMT0 7 S1M0 7 MUTE CDI1 6 S2M1 6 HPF0 CDI0 5 S2M0 5 HSR0 OPS1 4 FLS0 4 I2S0 OPS0 3 FLD1 3 LAW1 OPA1 2 FLD0 2 LAW0 OPA0 1 FLPD 1 DAPD VLPD 0 AGPD 0 ADPD CFG0 CFG1 CFG2 - 36 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY AUTO MUTE AND AUTO GAIN FUNCTIONS During playback, the signal passes through the Automatic Attenuator before it is filtered. The Automatic Attenuator will attenuate all signals at the noise level in order to reduce the noise during quiet pauses. During record, low level input signals are brought up by the Auto Gain function if the configuration bit D7 of CFG0 (AMT0) is set. This improves the signal to noise ratio of recorded low level input signals. If the configuration bit CFG0<7> (AMT0) is set to ZERO, all input levels are recorded with the same gain setting. The attack and release time of the Auto Gain and Auto Mute functions is set by the capacitor on the ACAP pin. The AGC cannot be used if the Auto Gain or Auto Mute function is enabled. Tattack 0,1504 x Vpeak Trelease 6.58 x Vpeak @ Cattcap=4.7 F Expand Gain (dB) 0 Gain (dB) 12 Compress -12 0 Vpp 0 0 Vpp - 37 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY VOLUME CONTROL DESCRIPTION VLPD 0 1 CONDITION Power Up Power Down VOL2 0 0 VLS1 VLS0 SOURCE 0 0 1 1 0 1 0 1 DAC OUT SUM2 SUM1 INP 0 0 1 1 1 1 VOL1 0 0 1 1 0 0 1 1 VOL0 0 1 0 1 0 1 0 1 ATTENUATION 0 dB 4 dB 8 dB 12 dB 16 dB 20 dB 24 dB 28 dB 15 CIG2 15 VLS1 15 X 14 CIG1 14 VLS0 14 X 13 CIG0 13 VOL2 13 X 12 AXG1 12 VOL1 12 CKD2 11 AXG0 11 VOL0 11 COG2 10 AXPD 10 S1S1 10 COG1 9 INS0 9 S1S0 9 COG0 8 OSPD 8 S1M1 8 CKDV 7 AMT0 7 S1M0 7 MUTE 6 CDI1 6 S2M1 6 HPF0 5 CDI0 5 S2M0 5 HSR0 4 OPS1 4 FLS0 4 I2S0 3 OPS0 3 FLD1 3 LAW1 2 OPA1 2 FLD0 2 LAW0 1 OPA0 1 FLPD 1 DAPD 0 VLPD 0 AGPD 0 ADPD CFG2 CFG1 CFG0 - 38 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY SPEAKER AND AUX OUT DESCRIPTION OPS1 0 0 1 1 OPS0 0 1 0 1 SOURCE VOL DAC OUT FILTO SUM2 OPA1 0 0 1 1 OPA0 SPKR DRIVE 0 1 0 1 Power Down 3.6 VP-P @ 150 23.5 mWatt @ 8 Power Down AUX OUT Power Down Power Down Power Down 1 VP-P Max @ 5 K 15 CIG2 15 VLS1 15 X 14 CIG1 14 VLS0 14 X 13 CIG0 13 VOL2 13 X 12 AXG1 12 VOL1 12 CKD2 11 AXG0 11 VOL0 11 COG2 10 AXPD 10 S1S1 10 COG1 9 INS0 9 S1S0 9 COG0 8 OSPD 8 S1M1 8 CKDV 7 AMT0 7 S1M0 7 MUTE 6 CDI1 6 S2M1 6 HPF0 5 CDI0 5 S2M0 5 HSR0 4 OPS1 4 FLS0 4 I2S0 3 OPS0 3 FLD1 3 LAW1 2 OPA1 2 FLD0 2 LAW0 1 OPA0 1 FLPD 1 DAPD 0 VLPD 0 AGPD 0 ADPD CFG2 CFG1 CFG0 - 39 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY MICROPHONE INPUTs The microphone inputs transfer the voice signal to the on-chip AGC preamplifier, or directly to the CODEC INPUT MUX, depending on the selected path. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p-p into the storage array from a typical electret microphone output of 2 to 20 mV p-p. The input impedance is typically 10k. The MICBS pin provides a 2.2V bias voltage for the external microphone only when the AGC is powered up. Using this regulated bias voltage results in less supply noise coupling into the MIC+ and MIC- pins compared to the situation in which the external microphone is powered up through the power supply. It also saves current during power down. The ACAP pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It should have a 4.7 F capacitor connected to ground. It cannot be left floating. This is because the capacitor is also used in the playback mode for the AutoMute circuit or when signal compression is chosen (AMT0 set). The AutoMute circuit reduces the amount of noise present in the output during quiet pauses. Tying the ACAP pin to ground gives maximum gain. Tying it to VCCA gives minimum gain for the AGC amplifier, but cancels the AutoMute function. MICBS MICROPHONE CDI1 0 0 1 1 CDI0 0 1 0 1 CODEC ADC INPUT INP SUM2 MIC No Input 2.2V Voltage 2.2V Voltage reference reference (AGPD) 1 AGPD CONDITION Power Up Power Down MIC+ MIC AGCCAP MIC IN MIC IN 1 0 1 AGC (AGPD) IN P SU IN M2 P+ SU M2 + ( 11 AXG0 11 VOL0 11 COG2 10 AXPD 10 S1S1 10 COG1 9 INS0 9 S1S0 9 COG0 8 OSPD 8 S1M1 8 CKDV CODEC INPUT MUX CDI0 2 CDI1 CODEC ADC IN 15 CIG2 15 VLS1 15 X 14 CIG1 14 VLS0 14 X 13 CIG0 13 VOL2 13 X 12 AXG1 12 VOL1 12 CKD2 7 AMT0 7 S1M0 7 MUTE 6 CDI1 6 S2M1 6 HPF0 5 CDI0 5 S2M0 5 HSR0 4 OPS1 4 FLS0 4 I2S0 3 OPS0 3 FLD1 3 LAW1 2 OPA1 2 FLD0 2 LAW0 1 OPA0 1 FLPD 1 DAPD 0 VLPD 0 AGPD 0 ADPD CFG2 CFG1 CFG0 - 40 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY DIGITAL MODE In the Digital Mode, it is important to understand that each group of digital operations must be preceded by the Digital Mode command (0XC0) and followed by the Exit Digital Mode command (0X40). No delay is required after these commands. Note that after any of these operations is completed, the device is powered down. Therefore, it will be required to issue the normal Power-Up command (0X80h) with a power-up delay (Tpud) before any analog operations can be performed following digital commands. WRITING DATA The Digital Write function allows the user to select a portion of the array to be used as digital memory. The partition between analog and digital memory is left up to the user. A page can only be either Digital or Analog, but not both. The minimum addressable block of memory in the digital mode is 1 block, or 64 bits, when reading or writing. The address sent to the device is the 11-bit row (or page) address with the 5-bit scan (or block) address. However, one must send a Digital Erase before attempting to change digital data on a page. This means that even when changing only one of the 32 blocks, all 32 will need to be rewritten to the page. After the address is entered, the data is sent in one-byte packets followed by an I C acknowledge generated by the chip. Data for each block is sent MSB first. The data transfer is ended when the 2 master generates an I C STOP condition. If only a partial block of data is sent before the STOP condition, zero is "written" in the remaining bytes; that is, they are left at the erase level. An erased page (row) will be read as all zeros. The device can buffer up to two blocks of data. If the device is unable to accept more data due to the internal write process, the SCL line will be held LOW indicating, to the master, to halt data transfer. If the device encounters an overflow condition, it 2 will respond by generating an interrupt condition and an I C Not Acknowledge signal after the last valid byte of data. Once data transfer is terminated, the device needs up to two cycles (64 us) to complete its internal write cycle before another command is sent. If an active command is sent before the internal cycle is finished, the I5216 will hold SCL LOW until the current command is finished. 2 READING DATA The Digital Read command utilizes the combined I C command format. That is, a command is sent to the chip using the write data direction. Then the data direction is reversed by sending a repeated start condition and the slave address with R/W set to one. After this, the slave device (I5216) begins to send data to the master until the master generates a Not Acknowledge. If the part encounters an overflow condition, the INT pin is pulled LOW. No other communication with the master is possible due to the master generating ACK signals. As with Digital Write, Digital Read can be done a "block" at a time. Thus, only 64 bits need to be read in each Digital Read command sequence. 2 ERASING DATA The Digital Erase command can only erase an entire page at a time. This means that the D0 or D1 command only needs to include the 11-bit page address; the 5-bit for block address are left at 00000. Once a page has been erased, each block may be written separately, 64 bits at a time. But, if a block has been previously written, then the entire page of 2048 bits must be erased in order to re-write (or change) a block. - 41 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY A sequence might look like: - read the entire page - store it in RAM - change the desired bit(s) - erase the page - write the new data from RAM to the entire page EXAMPLE COMMAND SEQUENCES Graphical representations of these operations follow each description. WRITE DIGITAL DATA: A single byte may be written to the Command Byte Register in order to power up the device, start or stop Analog Record (if no address information is needed), or do a Message Cueing function. For the normal digital addressed mode, the Registers are loaded as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. Host executes I C START. Send Slave Address with R/W bit = "0" (Write). Slave responds back with an ACK. Wait for SCL HIGH. Send Digital Mode command - 0X80h, 0XC0h Slave responds with an ACK. Wait for SCL HIGH. Send Slave Address command - 0X80h Slave responds with an ACK. Wait for SCL HIGH. Host sends a byte to Slave - (Command Byte = 00C9h). Slave responds with an ACK. Wait for SCL HIGH. Host sends a byte to Slave - (High Address Byte). Slave responds with an ACK. Wait for SCL HIGH. Host sends a byte to Slave - (Low Address Byte). Slave responds with an ACK Wait for SCL HIGH. Host sends a byte to Slave - (First 8 bits of digital information). Slave responds with an ACK. Wait for SCL HIGH. Steps 19, 20 and 21 are repeated until last byte is sent and acknowledged. 2 Send Exit Digital Mode Command - 0X80h, 0X40hHost executes I C STOP. 2 S SLAVE ADDRESS W A C9h A DATA A DATA A P Command - 42 High Addr. Low Addr. Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY READ DIGITAL DATA: For a normal digital read, the Registers are loaded as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. Host executes I C START. Send Slave Address with R/W bit = "0" (Write). Slave responds back with an ACK. Wait for SCL HIGH. Send Digital Mode command - 0X80h, 0XC9h Slave responds with an ACK. Wait for SCL HIGH Host sends a byte to Slave - (Command Byte = E1). Slave responds with an ACK. Wait for SCL HIGH. Host sends a byte to Slave - (High Address Byte). Slave responds with an ACK. Wait for SCL HIGH. Host sends a byte to Slave - (Low Address Byte). Slave responds with an ACK. Wait for SCL HIGH. Host sends repeat START. Host sends Slave Address with R/W bit = 1 (Reverses Data Direction). Slave responds with an ACK. Wait for SCL HIGH. Slave sends a byte to Host - (First 8 bits of digital information). Host responds with an ACK. Wait for SCL HIGH. Steps 20, 21 and 22 are repeated until last byte is sent and a NO ACK is returned. Host sends Slave Address with R/W bit = 0 (Reverses Data Direction) Slave responds with an ACK. Wait for SCL HIGH. Host sends Exit Digital Mode command. - 0X40 Slave responds with an ACK. Wait for SCL HIGH 2 Host executes I C STOP. 2 S SLAVE ADDRESS W A E1 A DATA A DATA N P Command High Addr. Low Addr. - 43 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY ERASE DIGITAL DATA: To erase digital information the following is done: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. Host executes I C START. Send Slave Address with R/W bit = "0" (Write). Slave responds back with an ACK. Wait for SCL HIGH. Send Digital Mode command - 0X80h, 0XC0h Slave responds with an ACK. Wait for SCL HIGH. Send Slave Address command - 0X80h Slave responds with an ACK. Wait for SCL HIGH. Host sends a Digital Erase command to Slave - (Command Byte = 0XD1h). Slave responds with an ACK. Wait for SCL HIGH. Host sends a byte to Slave - (High Address Byte = 0000h). Slave responds with an ACK. Wait for SCL HIGH. Host sends a byte to Slave - (Low Address Byte = 0XA0h). Erase row 5 in this example. Slave responds with an ACK Wait for SCL HIGH. 2 Host executes I C STOP. Host waits for RAC\ to go LOW and then back HIGH. 2 Host executes I C START. Send Exit Digital Mode Command - 0X80h, 0X40h Slave responds with an ACK. Wait for SCL HIGH 2 Host executes I C STOP. Erase starts on falling edge of Slave acknowledge 2 S SLAVE ADDRESS W A D1h A DATA A DATA A P Note 2 Command Byte High Addr. Byte Low Addr. Byte "N" RAC cycles Note 3. Last erased row Note 4. S SLAVE ADDRESS W A 80h A P Command Byte - 44 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY Notes: 1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low Address Byte will be ignored. 2 2. I C bus is released while erase proceeds. Other devices may use the bus until it is time to execute the STOP command that causes the end of the Erase operation. 3. Host processor must count RAC cycles to determine where the chip is in the erase process, one row per RAC cycle. RAC pulses LOW for 0.25 microsecond at the end of each erased row. The erase of the "next" row begins with the rising edge of RAC. See the Digital Erase RAC timing diagram on page 46. 4. When the erase of the last desired row begins, the following STOP command (Command Byte = 80 hex) must be issued. This command must be completely given, including receiving the ACK from the Slave before the RAC pin goes HIGH .25 microseconds before the end of the row. PIN DETAILS DIGITAL I/O PINS: SCL (SERIAL CLOCK LINE) The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor to Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged over the Serial Data Line. SDA (SERIAL DATA LINE) The Serial Data Line carries the data between devices on the I C interface. Data must be valid on this line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is a bidirectional line requiring a pull-up resistor to Vcc. 2 RAC (ROW ADDRESS CLOCK) RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency the duration of this period is 256 ms. there are 1888 pages of memory in the Winbond I5216 device. RAC stays HIGH for 248 ms and goes LOW for the remaining 8 ms before it reaches the end of the page. 1 ROW RAC Waveform During 8 KHz Operation 256 msec TRAC 8 msec TRACLO - 45 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY The RAC pin remains HIGH for 500 sec and stays LOW for 15.6 sec under the Message Cueing mode. See the Timing Parameters table on page 55 for RAC timing information at other sample rates. When a record command is first initiated, the RAC pin remains HIGH for an extra TRACLO period in order to load sample and hold circuits internal to the device. The RAC pin can be used for message management techniques. 1 ROW RAC Waveform During Message Cueing 500 usec TRAC 15.6 us TRACLO RAC Waveform During Digital Erase 1.25 sec .25 sec INT (Interrupt) INT is an open drain output pin. The Winbond I5216 Interrupt pin goes LOW and stays LOW when an Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or OVF generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ STATUS instruction that gives a status byte out the SDA line. MCLK (Master Clock Input) The Master clock input for the Winbond I5216 product has an internal pull-down device. Normally, the Winbond I5216 ChipCorder section is operated at one of four internal rates selected for its internal oscillator by the Sample Rate Select bits. If the internal oscillator is powered down (configuration bit OSPD set to ONE), the device is clocked through the MCLK pin as shown in the section I5216 Analog Structure (right half) description on page 36. - 46 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY Master Clock Input Table for ChipCorder Section FMCLK 13.824 MHz 20.48 MHz 27.648 MHz 40.96 MHz 13.824 MHz 20.48 MHz 27.648 MHz 40.96 MHz 13.824 MHz 20.48 MHz 27.648 MHz 40.96 MHz 13.824 MHz 20.48 MHz 27.648 MHz 40.96 MHz FLD1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FLD0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CKD2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CKDV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sample Rate 8.0 kHz 8.0 kHz 8.0 kHz 8.0 kHz 6.4 kHz 6.4 kHz 6.4 kHz 6.4 kHz 5.3 kHz 5.3 kHz 5.3 kHz 5.3 kHz 4.0 kHz 4.0 kHz 4.0 kHz 4.0 kHz Filter Knee 3.7 kHz 3.7 kHz 3.7 kHz 3.7 kHz 2.9 kHz 2.9 kHz 2.9 kHz 2.9 kHz 2.5 kHz 2.5 kHz 2.5 kHz 2.5 kHz 1.8 kHz 1.8 kHz 1.8 kHz 1.8 kHz Because the anti-aliasing and smoothing filters track the Sample Rate Select bits, one must, for optimum performance, maintain the external clock at one of the four possible frequencies shown in the table for Analog Structure (Right Half) description on page 36 AND set the Sample Rate Configuration bits to one of the four values in order to properly set the filters to their correct cutoff frequency as described in Analog Structure (Right Half) description on page 36. The duty cycle on the input clock is not critical when CKD2 is set to ONE, as the clock is immediately divided by two (internally). If the MCLK is not used, this input should be connected to VSSD. A0, A1 (Address Pins) These two pins are normally strapped for the desired address that the Winbond I5216 will have on the 2 I C serial interface. If there are four of these devices on the bus, then each must be strapped differently in order to allow the master device to address them individually. The possible addresses range from 80h to 87h, depending upon whether the device is being written to, or read from, by the host. The Winbond I5216 has a 7-bit slave address of which only A0 and A1 are pin programmable. The eighth bit (LSB) is the R/W bit. Thus, the address will be 1000 0xy0 or 1000 0xy1 - 47 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY ANALOG I/O PINS MIC+, MIC(Microphone Input +/-) The microphone input transfers the voice signal to the on-chip AGC preamplifier or directly to the CODEC A/D INPUT MUX, depending on the selected path. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p-p into the storage array from a typical electric microphone output of 2 to 20 mV p-p. The input impedance is typically 20 k differential and 13.3 k differential when the CODEC INPUT MUX MICIN path is selected. MICROPHONE INPUT 1.5k .1F MICBS 2.2V Voltage reference MIC+ Ra=10k (AGPD) MIC IN 1 Electret Microphone WM-54B Panasonic .1F 1.5k AGC MIC AGCCAP (AGPD) 1 4.7F CODEC INPUT MUX (CDI0 ) CDI1 2 CODEC ADC IN f - 3 dB = 1 2 Ra CCOUPLE ACAP (AGC Capacitor) This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It should have a 4.7 F capacitor connected to ground. It cannot be left floating. This is because the capacitor is also used in the playback mode for the AutoMute circuit or when signal compression is chosen (AMT0 is set to ONE). This circuit reduces the amount of noise present in the output during quiet pauses. Tying this pin to ground gives maximum gain. Tying it to VCCA gives minimum gain for the AGC amplifier, but cancels the AutoMute function. - 48 Publication Release Date: November 30, 2001 Revision A1 SUM2+ Rc=40k INP+ INP- SUM2- I5216 SERIES Advanced Information PRELIMINARY SP +, SP- (Speaker +/-) This is the speaker differential output circuit. It is designed to drive an 8 speaker connected across the speaker pins, up to a maximum of 23.5 mW RMS power. This stage has two selectable gains, 1.32 and 1.6, which can be chosen through the configuration registers. These pins are biased to approximately 1.2 VDC and, if used single-ended, must be capacitively coupled to their load. Do NOT ground the unused pin. AUX OUT (Auxiliary Output) The AUX OUT is an additional audio output pin to be used, for example, to drive the speaker circuit in a "car kit." It drives a minimum load of 5 k and up to a maximum of 1 V p-p. The AC signal is superimposed on approximately 1.2 VDC bias and must be capacitively coupled to the load. OPS1 0 0 1 1 OPS0 0 1 0 1 SOURCE VOL DAC OUT FILTO SUM2 OPA1 0 0 1 1 OPA0 SPKR DRIVE 0 1 0 1 Power Down 3.6 VP-P @ 150 23.5 mWatt @ 8 Power Down AUX OUT Power Down Power Down Power Down 1 VP-P Max @ 5 K 15 CIG2 15 VLS1 15 X 14 CIG1 14 VLS0 14 X 13 CIG0 13 VOL2 13 X 12 AXG1 12 VOL1 12 CKD2 11 AXG0 11 VOL0 11 COG2 10 AXPD 10 S1S1 10 COG1 9 INS0 9 S1S0 9 COG0 8 OSPD 8 S1M1 8 CKDV 7 AMT0 7 S1M0 7 MUTE 6 CDI1 6 S2M1 6 HPF0 5 CDI0 5 S2M0 5 HSR0 4 OPS1 4 FLS0 4 I2S0 3 OPS0 3 FLD1 3 LAW1 2 OPA1 2 FLD0 2 LAW0 1 OPA0 1 FLPD 1 DAPD 0 VLPD 0 AGPD 0 ADPD CFG2 CFG1 CFG0 - 49 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY AUX IN (Auxiliary Input) The AUX IN is an additional audio input to the Winbond I5216, such as from the microphone circuit in a mobile phone "car kit." This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). (See Aux In Amplifier Gain Settings Table below). Additional gain is available in 3 dB steps (controlled 2 by the I C interface) up to 9 dB. AUX IN INPUT MODES Internal to the device (1) Rb AUX IN Input AUX IN Input Amplifier Gain Setting 00 01 10 11 AXPD 0 1 Resistor Ratio (Rb/Ra) 40.1 / 40.1 47.0 / 33.2 53.5 / 26.7 59.2 / 21 Condition Power Up Power Down Gain 1.0 1.414 2.0 2.82 Gain (dB) 0 3 6 9 AUX IN AMPLIFIER GAIN SETTINGS 0TLP Input (2) VP-P 0.694 0.491 0.347 0.245 1. 2. 3. CFG0 AXG1 0 0 1 1 AXG0 0 1 0 1 Gain (1) Array In/Out VP-P 0.694 0.694 0.694 0.694 Speaker (3) Out VP-P 0.694 0.694 0.694 0.694 1.00 1.41 2.00 2.82 Gain from AUX IN to ARRAY IN 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping Differential - 50 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY POWER AND GROUND PINS VCCA, VCCD (Voltage Inputs) To minimize noise, the analog and digital circuits in the Winbond I5216 device use separate power busses. These +3 V busses lead to separate pins. Tie the VCCD pins together as close as possible, and decouple both supplies as near to the package as possible. VSSA, VSSD (Ground Inputs) The Winbond I5216 series utilizes separate analog and digital ground busses. The analog ground (VSSA) pins should be tied together as close to the package as possible, and connected through a lowimpedance path to power supply ground. The digital ground (VSSD) pin should be connected through a separate low impedance path to power supply ground. These ground paths should be large enough to ensure that the impedance between the VSSA pins and the VSSD pin is less than 3. The backside of the die is connected to VSSD through the substrate resistance. In a chip-on-board design, the die attach area must be connected to VSSD. NC (No Connect) These pins should not be connected to the board at any time. Connection of these pins to any signal, ground or VCC, may result in incorrect device behavior or cause damage to the device. - 51 - Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY SAMPLE PC LAYOUT FOR PDIP The PDIP package is illustrated from the top. PC board traces and the three chip capacitors are on the bottom side of the board. Note 2 V C C D MCLK 1 C1 C2 V S S D Note 3 (Digital Ground) Note 1 VSSA C1=C2=C3=0.1 uF chip Capacitors Note 1: VSSD traces should be kept separated back to the V supply feed SS point. Note 2: VCCD traces should be kept separated back to the V supply feed CC point. Note 3: The Digital and Analog grounds tie together at the power supply. The VCCA and VCCD supplies will also need filter capacitors (typ. 50 to 100 uF). C3 To VCCA Analog Ground Note 3 - 52 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (Packaged Parts) (1) Condition Junction temperature Storage temperature range Voltage Applied to any pin Voltage applied to any pin (Input current limited to +/-20 mA) Lead temperature (soldering VCC - VSS - 10 seconds) 150 C -65 C to +150 C (VSS - 0.3V) to (VCC + 0.3V) (VSS - 1.0V) to (VCC + 1.0V) 300 C -0.3V to +5.5V 0 0 0 0 Value 1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. ABSOLUTE MAXIMUM RATINGS (Die) (1) Condition Junction temperature Storage temperature range Voltage Applied to any pad VCC - VSS 150 C -65 C to +150 C (VSS - 0.3V) to (VCC + 0.3V) -0.3V to +5.5V 0 0 0 Value 1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. OPERATING CONDITIONS (Packaged Parts) Condition Commercial operating temperature range Extended operating temperature Industrial operating temperature Supply voltage (VCC) 1. Case temperature (2) (3) (1) (1) (1) Value 0 C to +70 C -20 C to +70 C -40 C to +85 C +2.7V to +3.3V 0V 0 0 0 0 0 0 Ground voltage (VSS) 2. VCC = VCCA = VCCD 3. VSS = VSSA = VSSD - 53 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY OPERATING CONDITIONS (Die) Condition Die operating temperature range Supply voltage (VCC) Ground voltage (VSS) 1. (2) (3) (1) Value 0 C to +50 C +2.7V to +3.3V 0V 0 0 Case temperature 2. VCC = VCCA = VCCD 3. VSS = VSSA = VSSD General Parameters Symbol VIL VIH VOL VOL1 VOH ICC Parameters Input Low Voltage Input High Voltage SCL, SDA, SDIO Output Low Voltage RAC, INT Output Low Voltage Output High Voltage VCC Current (Operating) - Playback & A/D + D/A - Record & A/D + D/A - CODEC A/D + D/A ISB IIL VCC Current (Standby) Input Leakage Current 30 36 20 1 50 56 30 10 +/-1 mA mA mA A A No Load No Load No Load (3) (3) (3) (3) Min (2) Typ (1) Max (2) Units V V Conditions VCC x 0.2 VCC x 0.8 0.4 0.4 VCC - 0.4 V V V IOL = 3 mA IOL = 1 mA IOL = -10 A 1. Typical values: TA = 25C and Vcc = 3.0 V. 2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. 3. VCCA and VCCD summed together. - 54 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY TIMING PARAMETERS Symbol FS Parameters Sampling Frequency Min (2) Typ (1) Max (2) Units kHz kHz kHz kHz kHz kHz kHz kHz min min min min min min min min msec msec msec msec Conditions (5) (5) (5) (5) Knee Point Knee Point Knee Point Knee Point (6) (6) (6) (6) (6) (6) (6) (6) (3)(7) (3)(7) (3)(7) (3)(7) 8.0 6.4 5.3 4.0 FCF Filter Knee 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) 3.7 2.9 2.5 1.8 8.05 10.06 12.15 16.1 8.05 10.06 12.15 16.1 1 1 1 1 TREC Record Duration 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TPLAY Playback Duration 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TPUD Power-Up Delay 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TSTOP OR PAUSE Stop or Pause Record or Play 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) 32 40 48 64 msec msec msec msec - 55 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY TIMING PARAMETERS (CONT'D) Symbol TRAC Parameters RAC Clock Period 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TRACLO RAC Clock Low Time 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TRACM RAC Clock Period Message Cueing Mode 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TRACML RAC Clock Low Time in Message Cueing Mode 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) THD Total Harmonic Distortion AUX IN to ARRAY, ARRAY to SPKR 1 1 2 2 % % in 500 625 750 1000 msec msec msec msec 8 10 12.1 16 msec msec msec msec 256 320 386 512 msec msec msec msec (9) (9) (9) (9) Min (2) Typ (1) Max (2) Units Conditions 15.6 19.5 23.4 31.2 msec msec msec msec @1 KHz at 0TLP, sample rate = 5.3 KHz - 56 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY ANALOG PARAMETERS MICROPHONE INPUT (14) Symbol VMIC+/VMIC (0TLP) Parameters MIC +/- Input Voltage MIC +/- input reference transmission level point (0TLP) MIC +/- Gain Tracking Microphone input resistance Microphone AGC Amplifier Range Microphone Bias Voltage MICBS Output Resistance Min (2) Typ ( 1)(14) Max (2) Units mV mV Conditions Peak-to-Peak Peak-to-Peak (4)(8) (4)(10) 300 208 AMIC (GT) RMIC AAGC VMICBS RMICBS +/-0.1 10 6 2.2 700 40 dB k dB V 1 kHz, +3 to -40 dB 0TLP Input MIC- and MIC+ pins Over 3-300 mV Range IMICBS = 0.0 mA AUX IN (14) Symbol VAUX IN VAUX IN (0TLP) AAUX IN (GA) AAUX IN (GT) RAUX IN Parameters AUX IN Input Voltage AUX IN (0TLP) Input Voltage AUX IN Gain Accuracy AUX IN Gain Tracking AUX IN Input Resistance Min (2) Typ (1)(14) Max 1.0 (2) Units V mV Conditions Peak-to-Peak (0 dB gain setting) Peak-to-Peak (0 dB gain setting) (11) 1000 Hz, +3 to -45 dB 0TLP Input, 0 dB setting Depending on AUX IN Gain 694.2 -0.5 +/-0.1 10 to 100 +0.5 dB dB k - 57 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY SPEAKER OUTPUTS (14) Symbol VSPHG Parameters SP+/- Output Voltage (High Gain Setting) SP+/- Output Load Imp. (Low Gain) SP+/- Output Load Imp. (High Gain) SP+/- Output Load Cap. SP+/- Output Bias Voltage (Analog Ground) Speaker Output DC Offset Power Supply Rejection Ratio Min (2) Typ (1)(14) Max 3.6 (2) Units V Conditions Peak-to-Peak, differential load = 150, OPA1, OPA0 = 01 OPA1, OPA0 = 10 OPA1, OPA0 = 01 RSPLG RSPHG CSP VSPAG VSPDCO PSRR 8 70 150 100 1.2 +/-100 -55 pF VDC mV DC dB With CODEC D/A IN to Speaker. Measured with a 1 kHz, 100 map sine wave input at VCC and VCC pins With 0TLP input to AUX (12) IN, 6 dB setting Differential load at 8 FR POUTLG Frequency Response (3003400 Hz) Power Output (Low Gain Setting) -0.25 23.5 +0.25 dB mW RMS AUX OUT (14) Symbol VAUX OUT RL CL VBIAS Parameters AUX OUT - Maximum Output Swing Minimum Load Impedance Maximum Load Capacitance AUX OUT Min (2) Typ (1)(14) Max 1.0 (2) Units V K Conditions 5k Load 5 100 1.2 pF VDC - 58 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY VOLUME CONTROL (14) Symbol AOUT Parameters Output Gain Absolute Gain Min (2) Typ (1)(14) Max (2) Units dB Conditions 8 steps of 4 dB, referenced to output AUX IN 1.0 kHz 0TLP, 6 dB gain setting measured differentially at SP+/- -28 to 0 -0.5 +0.5 dB 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Typical values: TA = 25C and Vcc = 3.0V. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions). Differential input mode. Nominal differential input is 208 mV p-p. (0TLP) Sampling frequency can vary as much as -6/+4 percent over the industrial temperature and voltage ranges. For greater stability, an external clock can be utilized (see Pin Descriptions). Playback and Record Duration can vary as much as -6/+4 percent over the industrial temperature and voltage ranges. For greater stability, an external clock can be utilized (see Pin Descriptions). Filter specification applies to the low pass filter. For optimal signal quality, this maximum limit is recommended. When a record command is sent, TRAC = TRAC + TRACLO on the first page addressed. The maximum signal level at any input is defined as 3.17 dB higher than the reference transmission level point. (0TLP) This is the point where signal clipping may begin. Measured at 0TLP point for each gain setting. See AUX IN table. 0TLP is the reference test level through inputs and outputs. See AUX IN table. Referenced to 0TLP input at 1 kHz, measured over 300 to 3,400 Hz bandwidth. For die, only typical values are applicable. - 59 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I2C INTERFACE TIMING STANDARD-MODE PARAMETER SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time condition for a repeated START SYMBOL MIN. 0 4.0 MAX. 100 FAST-MODE MIN. 0 0.6 MAX. 400 UNIT kHz ns fSCL tHD; STA tLOW tHIGH tSU; STA tSU; DAT tr tf tSU; STO tBUF Cb VnL VnH 4.7 4.0 4.7 250 4.0 4.7 0.1 VDD 0.2 VDD 1000 300 400 - 1.3 0.6 0.6 100 (1) (2) (2) 300 300 400 - ns ns ns ns ns ns ns ns pF V V Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus-free time between a STOP and START condition Capacitive load for each bus line Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) 20 + 0.1Cb 20 + 0.1Cb 0.6 1.3 0.1 VDD 0.2 VDD 1. A Fast-mode I C-interface device can be used in a Standard-mode I C-interface system, but the requirement tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. 2 2 If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line; tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode 2 I C -interface specification) before the SCL line is released. 2. Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times are allowed. - 60 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY CODEC PARAMETERS The internal CODEC meets the specification of the ITU-T G.714 recommendation in 8 kHz sampling mode. This specification is verified, using the MIC+/- and SPEAKER+/- pins as analog input and output. The CODEC /A-Law Compander meets the specification of the ITU-T G.711 /A-Law companding recommendation Symbol LABS TXMAX fch1 fcl1 fcl2 fMCLK DMCLK Parameters Absolute level Max. Transmit level High pass filter cut-off frequency Low pass filter cut-off frequency Low pass filter cut-off frequency Master clock frequency accuracy Master Clock Duty Cycle Min Typ 2 300 3400 Max Units Vrms Vpp Hz Hz Conditions 0 dBm0 = -2.5dBm @ 600 Mic+/Mic- differential @WS=8kHz, MCLK=13.824MHz @WS=8kHz, MCLK=13.824MHz @ WS=44.1kHz - 48kHz, MCLK=20.48MHz 4686 -500 48 5037 0 50 5100 +500 52 Hz ppm % - 61 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY TIMING DIAGRAMS I2C TIMING DIAGRAM STOP START t SU;DAT t f t r SDA SCL t f t t LOW HIGH t SU;STO t SCLK PLAYBACK AND STOP CYCLE tSTART SDA PLAY AT ADDR STOP tSTOP SCL DATA CLOCK PULSES STOP AUX IN AUX OUT - 62 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY EXAMPLE OF POWER UP COMMAND - 63 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I2S TIMING DIAGRAMS - 64 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I2S PARAMETERS (all values in nano seconds) Parameter Transmitter Lower Limit MIN Bit Clock period T High time tHC Low time tLC Rise time tRC Delay tdtr Hold time thtr Set-up time tsr Hold time thr 100 65 0 325 114 114 49 260 MAX Upper Limit MIN MAX Receiver Lower Limit MIN 325 114 114 MAX Upper Limit MIN MAX NOTES PCM TIMING DIAGRAMS - 65 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY PCM TIMING DIAGRAMS (CONT'D) - 66 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY PCM TIMING DIAGRAMS (CON'TD) - 67 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY PCM PARAMETERS PARAMETER Bit Clock Frequency Bit Clock Duty Cycle Word Sync. Frequency Word Sync. Frequency Rise Time Fall Time Hold Time for 2 of Bit clock nd SYMBOL 1/TSCK DC 1/TWSl 1/TWSh TIR TIF cycle THLD TXS TSX TRS TSR TSTSDI THDSDI TDV TDHI CONDITIONS SCK SCK WS @ low rate WS @ high rate SCK,SDI,SDIO,WS SCK,SDI,SDIO,WS MIN. 64 ----44.1 ----50 20 100 20 100 20 50 10 10 TYP. --50 8000 ------------------------- MAX. 3072 ----48 50 50 --------------120 120 UNIT kHz % Hertz kHz nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec SCK low to WS low SCK to WS WS to SCK SCK to WS WS to SCK ----SCK to SDIO SCK to SDIO Transmit Sync. Timing Receive Sync. Timing Setup Time for SDI valid Hold Time for SDI valid Output Delay Time for SDIO valid Output Delay Time for SDIO High Impedance - 68 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I2C SERIAL INTERFACE TECHNICAL INFORMATION CHARACTERISTICS OF THE I2C SERIAL INTERFACE The I C interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the interface bus is not busy. 2 BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal. START AND STOP CONDITIONS Both data and clock lines remain HIGH when the interface bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) SDA SCL data line stable; data valid change of data allowed 2 Bit transfer on the I C-bus handbook, full pagewidth SDA SDA SCL S START condition P STOP condition SCL MBC622 Definition of START and STOP conditions - 69 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY SYSTEM CONFIGURATION A device generating a message is a `transmitter'; a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices that are controlled by the master are the `slaves'. ACKNOWLEDGE The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the interface bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. In addition, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (setup and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. MICRO CONTROLLER LCD DRIVER STATIC RAM OR EEPROM SDA SCL GATE ARRAY ISD 5116 MBC645 Example of an I C-bus configuration using two microcontrollers 2 Data output by DATA OUTPUT transmitter BY TRANSMITTER Not acknowlwedge not acknowledge Data output by DATA receiverOUTPUT BY RECEIVER acknowledge Not acknowlwedge SCL from Master SCL FROM MASTER S Start condition 1 7 2 2 8 8 9 9 START condition clock pulse for Clock pulse for acknowledgement acknowledgement MBC602 Acknowledge on the I 2C-bus Acknowledge on the I C-bus Publication Release Date: November 30, 2001 Revision A1 2 - 70 I5216 SERIES Advanced Information PRELIMINARY I2C PROTOCOL Since the I C protocol allows multiple devices on the bus, each device must have an address. This address is known as a "Slave Address". A Slave Address consists of 7 bits, followed by a single bit that indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is being sent from the current bus master to the device being addressed. This single bit is a 0 for a Read cycle, which indicates that the data is being sent from the device being addressed to the current bus master. Before any data is transmitted on the I C interface, the current bus master must address the slave it st wishes to transfer data to or from. The Slave Address is always sent out as the 1 byte following the Start Condition sequence. An example of a Master transmitting an address to a ISD5216 slave is shown below. In this case, the Master is writing data to the slave and the R/W bit is "0", i.e. a Write cycle. All the bits transferred are from the Master to the Slave, except for the indicated Acknowledge bits. 2 2 Master Transmits to Slave Receiver (Write) Mode acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave S SLAVE ADDRESS WA COMMAND BYTE A High ADDR. BYTE A Low ADDR. BYTE A P Start Bit R/W Stop Bit A common procedure in the ISD5116 is the reading of the Status Bytes. The Read Status condition in the ISD5216 is triggered when the Master addresses the chip with its proper Slave Address, immediately followed by the R/W bit set to a "0" and without the Command Byte being sent. This is an example of the Master sending to the Slave, immediately followed by the Slave sending data back to the Master. The "N" not-acknowledge cycle from the Master ends the transfer of data from the Slave. Master Reads from Slave immediately after first byte (Read Mode) acknowledgement from slave From Slave S SL AVE ADDRESS R A STATUS W ORD A From Slave High ADDR. BYTE A From Slave Low ADDR BYTE N P From Master Start Bit From Master R/W From Master acknowledgement from Master acknowledgement from Master Stop Bit From Master not-acknowledged from Master - 71 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY Another common operation in the ISD5216 is the reading of digital data from the chip's memory array 2 at a specific address. This requires the I C interface Master to first send an address to the ISD5116 2 Slave device, and then receive data from the Slave in a single I C operation. To accomplish this, the data direction R/W bit must be changed in the middle of the command. The following example shows the Master sending the Slave address, then sending a Command Byte and 2 bytes of address data to the ISD5216, and then immediately changing the data direction and reading some number of bytes from the chip's digital array. An unlimited number of bytes can be read in this operation. The "N" notacknowledge cycle from the Master forces the end of the data transfer from the Slave. The following example details the transfer explained in the section on page 41 of this datasheet. Master Reads from the Slave after setting data address in Slave (Write data address, READ Data) acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave S SLAVE ADDRESS WA COMMAND BYTE A High ADDR. BYTE A Low ADDR. BYTE A Start Bit From Master R/W From Master acknowledgement from slave From Slave S SLAVE ADDRESS R A 8 BITS of DATA A From Slave 8 BITS of DATA A From Slave 8 BITS of DATA N P From Master Start Bit From Master R/W From Master acknowledgement from Master acknowledgement from Master not-acknowled from Master Stop Bit From Master - 72 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I2S SERIAL INTERFACE TECHNICAL INFORMATION 2 THE I BUS As shown in the following figure, the bus has three lines: * continuous serial clock (SCK) * word select (WS) * serial data (SD)and the device generating SCK and WS is the master. Simple System Configurations and Basic Interface Timing SERIAL DATA Serial data is transmitted in two's complement with the MSB first. The MSB is transmitted first because the transmitter and receiver may have different word lengths. It isn't necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. When the system word length is greater than the transmitter word length, the word is truncated (least significant data bits are set to `0') for data transmission. If the receiver is sent more bits than its word length, the bits after the LSB are ignored. On the other hand, if the receiver is sent fewer bits than its word length, the missing bits are set to zero internally. And so, the MSB has a fixed position, whereas the position of the LSB depends on the word length. The transmitter always sends the MSB of the next word one clock period after the WS changes. - 73 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY Serial data sent by the transmitter may be synchronized with either the trailing (HIGH-to-LOW) or the leading (LOW-to-HIGH) edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge (see figure below ). Note that the specifications are defined by the transmitter speed. The specification of the receiver has to be able to match the performance of the transmitter. - 74 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY WORD SELECT The word select line indicates the channel being transmitted: * WS = 0; channel 1 (left) * WS = 1; channel 2 (right) WS may change either on a trailing or leading edge of the serial clock, but it doesn't need to be symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The WS line changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the 2 receiver to store the previous word and clear the input for the next word (see figure Timing for I S Transmitter on previous page.) TIMING In the I S format, any device can act as the system master by providing the necessary clock signals. A slave will usually derive its internal clock signal from an external clock input. This means, taking into account the propagation delays between master clock and the data and/or word-select signals, that the total delay is simply the sum of: * the delay between the external (master) clock and the slave's internal clock; and * the delay between the internal clock and the data and/or word-select signals. For data and word-select inputs, the external to internal clock delay is of no consequence because it 2 only lengthens the effective set-up time (see figure Timing for I S Transmitter on previous page.) The major part of the time margin is to accommodate the difference between the propagation delay of the transmitter, and the time required to set up the receiver. All timing requirements are specified relative to the clock period or to the minimum allowed clock period of a device. This means that higher data rates can be used in the future. 2 Timing for I2S Receiver T = clock period TR = minimum allowed clock period for transmitter T > TR Note that the specifications are defined by the transmitter speed. The specification of the receiver has to be able to match the performance of the transmitter. - 75 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY S Parameters (all values in nanoseconds) Parameter Transmitter Lower Limit MIN Bit Clock period T High time tHC Low time tLC Rise time tRC Delay tdtr Hold time thtr Set-up time tsr Hold time thr 100 65 0 325 114 114 49 260 MAX Upper Limit MIN MAX Receiver Lower Limit MIN 325 114 114 MAX Upper Limit MIN MAX NOTES Voltage Level Specification Output Levels V L < 0.4V V H > 2.4V both levels able to drive one standard TTL input (I IL = -1.6mA and I IH = 0.04mA). Input Levels V IL = 0.8V V IH = 2.0V Note: At present, TTL is considered a standard for logic levels. As other IC (LSI) technologies become popular, other levels will also be supported. - 76 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY DEVICE PHYSICAL DIMENSIONS PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE E DIMENSIONS A B 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 G F C E D H I J PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE E DIMENSIONS INCHES M in A B C D E F G H I J 0.037 0 0.020 0.004 0 M ILLIM ETERS M ax 0.535 0.469 0.319 0.006 0.011 0.041 6 0.028 0.008 0 Nom 0.528 0.465 0.315 0.009 0.0217 0.039 3 0.022 0 M in 13.20 11.70 7.90 0.05 0.17 0.95 0 0.50 0.10 0 Nom 13.40 11.80 8.00 0.22 0.55 1.00 3 0.55 0 M ax 13.60 11.90 8.10 0.15 0.27 1.05 6 0.70 0.21 0 0.520 0.461 0.311 0.002 0.007 - 77 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) DIMENSIONS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A G C B D E F H PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) DIMENSIONS INCHES Min A B C D E F G H Note: 0.400 0.024 0.701 0.097 0.292 0.005 0.014 Nom 0.706 0.101 0.296 0.009 0.016 0.050 0.406 0.032 0.410 0.040 10.16 0.61 Max 0.711 0.104 0.299 0.0115 0.019 Min 17.81 2.46 7.42 0.127 0.35 MILLIMETERS Nom 17.93 2.56 7.52 0.22 0.41 1.27 10.31 0.81 10.41 1.02 Max 18.06 2.64 7.59 0.29 0.48 Lead coplanarity to be within 0.004 inches. - 78 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY - 79 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY DIE BONDING PHYSICAL LAYOUT I5216 DEVICE PIN/PAD LOCATIONS WITH RESPECT TO DIE CENTER IN MICRON (M) PIN VSSD VSSD AD0 SDA AD1 SCL VCCD VCCD MCLK INT RAC SDIO SDI VSSA VSSA MIC+ MICMICBS ACAP SPVSSA VSSA SP+ VCCA VCCA AUX IN AUX OUT SCK WS Pin Name VSS Digital Ground VSS Digital Ground Address 0 Serial Data Address Address 1 Serial Clock Line VCC Digital Supply Voltage VCC Digital Supply Voltage External Clock Input Interrupt Row Address Clock Serial Data Input Output Serial Data Input VSS Analog Ground " " " X Axis -1880.70 -1709.10 -1407.20 -1066.00 -743.70 -428.60 -156.50 58.90 246.80 554.10 1029.00 1362.60 1679.50 1840.55 -2027.80 -1824.20 -1628.60 -1327.95 -905.70 -373.50 -39.90 50.10 383.70 717.30 807.30 1073.00 1325.95 1634.65 1896.25 Y Axis 4721.30 4721.30 4721.30 4721.30 4721.30 4721.30 4721.30 4721.30 4721.30 4720.50 4721.30 4721.30 4721.30 4721.30 -4716.20 -4716.20 -4716.20 -4716.20 -4716.20 -4716.20 -4716.20 -4716.20 -4716.20 -4716.20 -4716.20 -4716.20 -4716.20 -4716.20 -4716.20 Non-inverting Microphone Input Inverting Microphone Input Microphone Bias Voltage AGC/AutoMute Cap Speaker Negative VSS Analog Ground VSS Analog Ground Speaker Positive VCC Analog Supply Voltage VCC Analog Supply Voltage Auxiliary Input Auxiliary Output Serial Data Clock Word Select - 80 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY I5216 SERIES BONDING PHYSICAL LAYOUT VSSD VSSD A0 SDA A1 SCL V CCD V CCD (1) (UNPACKAGED DIE) RAC SDIO SDI VSSA MCLK INT I5216 Series Die Dimensions X: 4380 m Y: (3) I5216 Series Die Dimensions X: 4380 Y: 9880 m m (3) Die Thickness Die Thickness 988 9880m I5216 90 x 90 Pad Opening (min) m 292.1 m Opening m + 12.7 Pad 90x 90 m 3.5 x 3.5 mils 292.1m + 12.7 m 3.5 x 3.5 mils VSSA MIC+ MIC - MICBS ACAP SP- VSSA(2) SP+ VCCA (2) AUXIN AUXOUT SCK WS 1. 2. The backside of die is internally connected to Vss. It MUST NOT be connected to any other potential or damage may occur. Double bond recommended. This figure reflects the current die thickness. Please contact Winbond as this thickness may change in the future. Publication Release Date: November 30, 2001 Revision A1 - 81 I5216 SERIES Advanced Information PRELIMINARY ORDERING INFORMATION WINBOND PART NUMBER DESCRIPTION I5216-_ _ Product Family I5216 Product (8- to 16-minute durations) Special Temperature Field: Blank D I = or = = Commercial Packaged (0C to +70C) Commercial Die (0C to +50C) Extended (-20C to +70C) Industrial (-40C to +85C) Package Type: E S P = = = = 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 28-Lead 0.300-Inch Plastic Small Outline Package (SOIC) 28-Lead Die 0.600-Inch Plastic Dual Inline Package (PDIP) X - 82 Publication Release Date: November 30, 2001 Revision A1 I5216 SERIES Advanced Information PRELIMINARY When ordering I5216 series devices, please refer to the following valid part numbers. Part Number I5216E I5216ED I5216EI I5216S I5216SD I5216SI I5216P I5216X Chip scale package is available upon customer's request. For the latest product information, access Winbond's worldwide website at http://www.winbondusa.com Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East. Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 83 Publication Release Date: November 30, 2001 Revision A1 |
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